]> git.sur5r.net Git - u-boot/blobdiff - drivers/usb/host/ehci-exynos.c
Merge branch 'master' of git://git.denx.de/u-boot-atmel
[u-boot] / drivers / usb / host / ehci-exynos.c
index 66b4de0b2d05d7a33ca6a11acabeb8fdf1d2537a..6fdbf5724f4a6527757d8cec692c9a59c7529b6a 100644 (file)
@@ -85,12 +85,9 @@ static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos)
 }
 #endif
 
-/* Setup the EHCI host controller. */
-static void setup_usb_phy(struct exynos_usb_phy *usb)
+static void exynos5_setup_usb_phy(struct exynos_usb_phy *usb)
 {
-       set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
-
-       set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
+       u32 hsic_ctrl;
 
        clrbits_le32(&usb->usbphyctrl0,
                        HOST_CTRL0_FSEL_MASK |
@@ -112,6 +109,32 @@ static void setup_usb_phy(struct exynos_usb_phy *usb)
        clrbits_le32(&usb->usbphyctrl0,
                        HOST_CTRL0_LINKSWRST |
                        HOST_CTRL0_UTMISWRST);
+
+       /* HSIC Phy Setting */
+       hsic_ctrl = (HSIC_CTRL_FORCESUSPEND |
+                       HSIC_CTRL_FORCESLEEP |
+                       HSIC_CTRL_SIDDQ);
+
+       clrbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
+       clrbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
+
+       hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK)
+                               << HSIC_CTRL_REFCLKDIV_SHIFT)
+                       | ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK)
+                               << HSIC_CTRL_REFCLKSEL_SHIFT)
+                       | HSIC_CTRL_UTMISWRST);
+
+       setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
+       setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
+
+       udelay(10);
+
+       clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST |
+                                       HSIC_CTRL_UTMISWRST);
+
+       clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST |
+                                       HSIC_CTRL_UTMISWRST);
+
        udelay(20);
 
        /* EHCI Ctrl setting */
@@ -122,9 +145,37 @@ static void setup_usb_phy(struct exynos_usb_phy *usb)
                        EHCICTRL_ENAINCR16);
 }
 
-/* Reset the EHCI host controller. */
-static void reset_usb_phy(struct exynos_usb_phy *usb)
+static void exynos4412_setup_usb_phy(struct exynos4412_usb_phy *usb)
 {
+       writel(CLK_24MHZ, &usb->usbphyclk);
+
+       clrbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
+               PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
+               PHYPWR_NORMAL_MASK_PHY0));
+
+       setbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
+       udelay(10);
+       clrbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST));
+}
+
+static void setup_usb_phy(struct exynos_usb_phy *usb)
+{
+       set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
+
+       set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
+
+       if (cpu_is_exynos5())
+               exynos5_setup_usb_phy(usb);
+       else if (cpu_is_exynos4())
+               if (proid_is_exynos4412())
+                       exynos4412_setup_usb_phy((struct exynos4412_usb_phy *)
+                                                usb);
+}
+
+static void exynos5_reset_usb_phy(struct exynos_usb_phy *usb)
+{
+       u32 hsic_ctrl;
+
        /* HOST_PHY reset */
        setbits_le32(&usb->usbphyctrl0,
                        HOST_CTRL0_PHYSWRST |
@@ -133,6 +184,33 @@ static void reset_usb_phy(struct exynos_usb_phy *usb)
                        HOST_CTRL0_FORCESUSPEND |
                        HOST_CTRL0_FORCESLEEP);
 
+       /* HSIC Phy reset */
+       hsic_ctrl = (HSIC_CTRL_FORCESUSPEND |
+                       HSIC_CTRL_FORCESLEEP |
+                       HSIC_CTRL_SIDDQ |
+                       HSIC_CTRL_PHYSWRST);
+
+       setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
+       setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
+}
+
+static void exynos4412_reset_usb_phy(struct exynos4412_usb_phy *usb)
+{
+       setbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 |
+               PHYPWR_NORMAL_MASK_HSIC1 | PHYPWR_NORMAL_MASK_PHY1 |
+               PHYPWR_NORMAL_MASK_PHY0));
+}
+
+/* Reset the EHCI host controller. */
+static void reset_usb_phy(struct exynos_usb_phy *usb)
+{
+       if (cpu_is_exynos5())
+               exynos5_reset_usb_phy(usb);
+       else if (cpu_is_exynos4())
+               if (proid_is_exynos4412())
+                       exynos4412_reset_usb_phy((struct exynos4412_usb_phy *)
+                                                usb);
+
        set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
 }
 
@@ -158,12 +236,15 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 
 #ifdef CONFIG_OF_CONTROL
        /* setup the Vbus gpio here */
-       if (!fdtdec_setup_gpio(&ctx->vbus_gpio))
+       if (fdt_gpio_isvalid(&ctx->vbus_gpio) &&
+           !fdtdec_setup_gpio(&ctx->vbus_gpio))
                gpio_direction_output(ctx->vbus_gpio.gpio, 1);
 #endif
 
        setup_usb_phy(ctx->usb);
 
+       board_usb_init(index, init);
+
        *hccr = ctx->hcd;
        *hcor = (struct ehci_hcor *)((uint32_t) *hccr
                                + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));