]> git.sur5r.net Git - u-boot/blobdiff - drivers/usb/host/ehci-marvell.c
Merge branch 'spi' of git://git.denx.de/u-boot-x86
[u-boot] / drivers / usb / host / ehci-marvell.c
index 6300587db02b37a9b4e809d10d6b9a3eb0e30720..2b73e4ad6abece9784b11aa55812aabff13285d4 100644 (file)
 #include <asm/io.h>
 #include <usb.h>
 #include "ehci.h"
-#include "ehci-core.h"
 #include <asm/arch/cpu.h>
+
+#if defined(CONFIG_KIRKWOOD)
 #include <asm/arch/kirkwood.h>
+#elif defined(CONFIG_ORION5X)
+#include <asm/arch/orion5x.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
 
-#define rdl(off)       readl(KW_USB20_BASE + (off))
-#define wrl(off, val)  writel((val), KW_USB20_BASE + (off))
+#define rdl(off)       readl(MVUSB0_BASE + (off))
+#define wrl(off, val)  writel((val), MVUSB0_BASE + (off))
 
 #define USB_WINDOW_CTRL(i)     (0x320 + ((i) << 4))
 #define USB_WINDOW_BASE(i)     (0x324 + ((i) << 4))
 static void usb_brg_adrdec_setup(void)
 {
        int i;
-       u32 size, attrib;
+       u32 size, base, attrib;
 
        for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 
                /* Enable DRAM bank */
                switch (i) {
                case 0:
-                       attrib = KWCPU_ATTR_DRAM_CS0;
+                       attrib = MVUSB0_CPU_ATTR_DRAM_CS0;
                        break;
                case 1:
-                       attrib = KWCPU_ATTR_DRAM_CS1;
+                       attrib = MVUSB0_CPU_ATTR_DRAM_CS1;
                        break;
                case 2:
-                       attrib = KWCPU_ATTR_DRAM_CS2;
+                       attrib = MVUSB0_CPU_ATTR_DRAM_CS2;
                        break;
                case 3:
-                       attrib = KWCPU_ATTR_DRAM_CS3;
+                       attrib = MVUSB0_CPU_ATTR_DRAM_CS3;
                        break;
                default:
                        /* invalide bank, disable access */
@@ -67,15 +73,16 @@ static void usb_brg_adrdec_setup(void)
                        break;
                }
 
-               size = kw_sdram_bs(i);
+               size = gd->bd->bi_dram[i].size;
+               base = gd->bd->bi_dram[i].start;
                if ((size) && (attrib))
                        wrl(USB_WINDOW_CTRL(i),
-                               KWCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
-                                       attrib, KWCPU_WIN_ENABLE));
+                               MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
+                                       attrib, MVCPU_WIN_ENABLE));
                else
-                       wrl(USB_WINDOW_CTRL(i), KWCPU_WIN_DISABLE);
+                       wrl(USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
 
-               wrl(USB_WINDOW_BASE(i), kw_sdram_bar(i));
+               wrl(USB_WINDOW_BASE(i), base);
        }
 }
 
@@ -83,17 +90,17 @@ static void usb_brg_adrdec_setup(void)
  * Create the appropriate control structures to manage
  * a new EHCI host controller.
  */
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
        usb_brg_adrdec_setup();
 
-       hccr = (struct ehci_hccr *)(KW_USB20_BASE + 0x100);
-       hcor = (struct ehci_hcor *)((uint32_t) hccr
-                       + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+       *hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
+       *hcor = (struct ehci_hcor *)((uint32_t) *hccr
+                       + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 
-       debug("Kirkwood-ehci: init hccr %x and hcor %x hc_length %d\n",
-               (uint32_t)hccr, (uint32_t)hcor,
-               (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+       debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
+               (uint32_t)*hccr, (uint32_t)*hcor,
+               (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
 
        return 0;
 }
@@ -102,7 +109,7 @@ int ehci_hcd_init(void)
  * Destroy the appropriate control structures corresponding
  * the the EHCI host controller.
  */
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
 {
        return 0;
 }