arm: mvebu: Enable USB EHCI support on Armada XP

[u-boot] / drivers / usb / host / ehci-marvell.c

diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c
index 52c43fdc5aaa1fdc2a99ed3177c65c35b3a2c979..fda812e94c50c61bb0b7e9c5d10d52216d1d9cb0 100644 (file)
--- a/drivers/usb/host/ehci-marvell.c
+++ b/drivers/usb/host/ehci-marvell.c
@@ -10,19 +10,17 @@
 #include <asm/io.h>
 #include <usb.h>
 #include "ehci.h"
+#include <linux/mbus.h>
 #include <asm/arch/cpu.h>
 
 #if defined(CONFIG_KIRKWOOD)
-#include <asm/arch/kirkwood.h>
+#include <asm/arch/soc.h>
 #elif defined(CONFIG_ORION5X)
 #include <asm/arch/orion5x.h>
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define rdl(off)       readl(MVUSB0_BASE + (off))
-#define wrl(off, val)  writel((val), MVUSB0_BASE + (off))
-
 #define USB_WINDOW_CTRL(i)     (0x320 + ((i) << 4))
 #define USB_WINDOW_BASE(i)     (0x324 + ((i) << 4))
 #define USB_TARGET_DRAM                0x0
@@ -30,6 +28,47 @@ DECLARE_GLOBAL_DATA_PTR;
 /*
  * USB 2.0 Bridge Address Decoding registers setup
  */
+#ifdef CONFIG_ARMADA_XP
+
+/*
+ * Armada XP and Armada 38x have different base addresses for
+ * the USB 2.0 EHCI host controller. So we need to provide
+ * a mechnism to support both here.
+ */
+#define MVUSB0_BASE                                    \
+       (mvebu_soc_family() == MVEBU_SOC_A38X ?         \
+        MVEBU_USB20_BASE : MVEBU_AXP_USB_BASE)
+
+/*
+ * Once all the older Marvell SoC's (Orion, Kirkwood) are converted
+ * to the common mvebu archticture including the mbus setup, this
+ * will be the only function needed to configure the access windows
+ */
+static void usb_brg_adrdec_setup(void)
+{
+       const struct mbus_dram_target_info *dram;
+       int i;
+
+       dram = mvebu_mbus_dram_info();
+
+       for (i = 0; i < 4; i++) {
+               writel(0, MVUSB0_BASE + USB_WINDOW_CTRL(i));
+               writel(0, MVUSB0_BASE + USB_WINDOW_BASE(i));
+       }
+
+       for (i = 0; i < dram->num_cs; i++) {
+               const struct mbus_dram_window *cs = dram->cs + i;
+
+               /* Write size, attributes and target id to control register */
+               writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
+                      (dram->mbus_dram_target_id << 4) | 1,
+                      MVUSB0_BASE + USB_WINDOW_CTRL(i));
+
+               /* Write base address to base register */
+               writel(cs->base, MVUSB0_BASE + USB_WINDOW_BASE(i));
+       }
+}
+#else
 static void usb_brg_adrdec_setup(void)
 {
        int i;
@@ -60,15 +99,17 @@ static void usb_brg_adrdec_setup(void)
                size = gd->bd->bi_dram[i].size;
                base = gd->bd->bi_dram[i].start;
                if ((size) && (attrib))
-                       wrl(USB_WINDOW_CTRL(i),
-                               MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
-                                       attrib, MVCPU_WIN_ENABLE));
+                       writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
+                                                  attrib, MVCPU_WIN_ENABLE),
+                               MVUSB0_BASE + USB_WINDOW_CTRL(i));
                else
-                       wrl(USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
+                       writel(MVCPU_WIN_DISABLE,
+                              MVUSB0_BASE + USB_WINDOW_CTRL(i));
 
-               wrl(USB_WINDOW_BASE(i), base);
+               writel(base, MVUSB0_BASE + USB_WINDOW_BASE(i));
        }
 }
+#endif
 
 /*
  * Create the appropriate control structures to manage