/*
* Copyright (c) 2011 The Chromium OS Authors.
- * Copyright (c) 2009-2013 NVIDIA Corporation
+ * Copyright (c) 2009-2015 NVIDIA Corporation
* Copyright (c) 2013 Lucas Stach
*
* SPDX-License-Identifier: GPL-2.0+
#endif
#endif
-#ifndef CONFIG_DM_USB
-enum {
- USB_PORTS_MAX = 3, /* Maximum ports we allow */
-};
-#endif
-
/* Parameters we need for USB */
enum {
PARAM_DIVN, /* PLL FEEDBACK DIVIDer */
USB_CTLR_T20,
USB_CTLR_T30,
USB_CTLR_T114,
+ USB_CTLR_T210,
USB_CTRL_COUNT,
};
unsigned ulpi:1; /* 1 if port has external ULPI transceiver */
unsigned enabled:1; /* 1 to enable, 0 to disable */
unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
-#ifndef CONFIG_DM_USB
- unsigned initialized:1; /* has this port already been initialized? */
-#endif
enum usb_ctlr_type type;
enum usb_init_type init_type;
enum dr_mode dr_mode; /* dual role mode */
struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */
};
-#ifndef CONFIG_DM_USB
-static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */
-static unsigned port_count; /* Number of available ports */
-#endif
-
/*
* This table has USB timing parameters for each Oscillator frequency we
* support. There are four sets of values:
{ 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
{ 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
{ 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 },
- { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
+ { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 },
+ { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 },
+ { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }
};
static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
{ 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 },
{ 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 },
{ 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 },
- { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
+ { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 },
+ { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 },
+ { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }
};
static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
{ 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 },
{ 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 },
{ 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 },
- { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB }
+ { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 11 },
+ { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 },
+ { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }
+};
+
+/* NOTE: 13/26MHz settings are N/A for T210, so dupe 12MHz settings for now */
+static const unsigned T210_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
+ /* DivN, DivM, DivP, KCP, KVCO, Delays Debounce, Bias */
+ { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 32500, 5 },
+ { 0x019, 0x01, 0x01, 0x0, 0, 0x03, 0x4B, 0x0C, 0xBB, 48000, 8 },
+ { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 },
+ { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 65000, 5 },
+ { 0x019, 0x02, 0x01, 0x0, 0, 0x05, 0x96, 0x18, 0x177, 96000, 15 },
+ { 0x028, 0x04, 0x01, 0x0, 0, 0x04, 0x66, 0x09, 0xFE, 120000, 20 }
};
/* UTMIP Idle Wait Delay */
static const u8 utmip_hs_sync_start_delay = 9;
struct fdt_usb_controller {
- /* TODO(sjg@chromium.org): Remove when we only use driver model */
- int compat;
/* flag to determine whether controller supports hostpc register */
u32 has_hostpc:1;
const unsigned *pll_parameter;
static struct fdt_usb_controller fdt_usb_controllers[USB_CTRL_COUNT] = {
{
- .compat = COMPAT_NVIDIA_TEGRA20_USB,
.has_hostpc = 0,
.pll_parameter = (const unsigned *)T20_usb_pll,
},
{
- .compat = COMPAT_NVIDIA_TEGRA30_USB,
.has_hostpc = 1,
.pll_parameter = (const unsigned *)T30_usb_pll,
},
{
- .compat = COMPAT_NVIDIA_TEGRA114_USB,
.has_hostpc = 1,
.pll_parameter = (const unsigned *)T114_usb_pll,
},
+ {
+ .has_hostpc = 1,
+ .pll_parameter = (const unsigned *)T210_usb_pll,
+ },
};
/*
UTMIP_DEBOUNCE_CFG0_MASK,
timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
+ if (timing[PARAM_DEBOUNCE_A_TIME] > 0xFFFF) {
+ clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
+ UTMIP_DEBOUNCE_CFG0_MASK,
+ (timing[PARAM_DEBOUNCE_A_TIME] >> 1)
+ << UTMIP_DEBOUNCE_CFG0_SHIFT);
+ clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
+ UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK,
+ 1 << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT);
+ }
+
setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
/* Disable battery charge enabling bit */
static void config_clock(const u32 timing[])
{
+ debug("%s: DIVM = %d, DIVN = %d, DIVP = %d, cpcon/lfcon = %d/%d\n",
+ __func__, timing[PARAM_DIVM], timing[PARAM_DIVN],
+ timing[PARAM_DIVP], timing[PARAM_CPCON], timing[PARAM_LFCON]);
+
clock_start_pll(CLOCK_ID_USB,
timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP],
timing[PARAM_CPCON], timing[PARAM_LFCON]);
}
-static int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config)
+static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config)
{
+ const void *blob = gd->fdt_blob;
+ int node = dev->of_offset;
const char *phy, *mode;
- config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
+ config->reg = (struct usb_ctlr *)dev_get_addr(dev);
mode = fdt_getprop(blob, node, "dr_mode", NULL);
if (mode) {
if (0 == strcmp(mode, "host"))
return -1;
}
-#ifndef CONFIG_DM_USB
- /* skip init, if the port is already initialized */
- if (config->initialized && config->init_type == init)
- return 0;
-#endif
-
debug("%d, %d\n", config->utmi, config->ulpi);
if (config->utmi)
ret = init_utmi_usb_controller(config, init);
.powerup_fixup = tegra_ehci_powerup_fixup,
};
-#ifndef CONFIG_DM_USB
-/*
- * process_usb_nodes() - Process a list of USB nodes, adding them to our list
- * of USB ports.
- * @blob: fdt blob
- * @node_list: list of nodes to process (any <=0 are ignored)
- * @count: number of nodes to process
- * @id: controller type (enum usb_ctlr_type)
- *
- * Return: 0 - ok, -1 - error
- */
-static int process_usb_nodes(const void *blob, int node_list[], int count,
- enum usb_ctlr_type id)
-{
- struct fdt_usb config;
- int node, i;
- int clk_done = 0;
-
- port_count = 0;
- for (i = 0; i < count; i++) {
- if (port_count == USB_PORTS_MAX) {
- printf("tegrausb: Cannot register more than %d ports\n",
- USB_PORTS_MAX);
- return -1;
- }
-
- debug("USB %d: ", i);
- node = node_list[i];
- if (!node)
- continue;
- if (fdt_decode_usb(blob, node, &config)) {
- debug("Cannot decode USB node %s\n",
- fdt_get_name(blob, node, NULL));
- return -1;
- }
- if (!clk_done) {
- config_clock(get_pll_timing(
- &fdt_usb_controllers[id]));
- clk_done = 1;
- }
- config.type = id;
- config.initialized = 0;
-
- /* add new USB port to the list of available ports */
- port[port_count++] = config;
- }
-
- return 0;
-}
-
-int usb_process_devicetree(const void *blob)
-{
- int node_list[USB_PORTS_MAX];
- int count, err = 0;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(fdt_usb_controllers); i++) {
- count = fdtdec_find_aliases_for_id(blob, "usb",
- fdt_usb_controllers[i].compat, node_list,
- USB_PORTS_MAX);
- if (count) {
- err = process_usb_nodes(blob, node_list, count, i);
- if (err)
- printf("%s: Error processing USB node!\n",
- __func__);
- return err;
- }
- }
-
- return err;
-}
-
-/**
- * Start up the given port number (ports are numbered from 0 on each board).
- * This returns values for the appropriate hccr and hcor addresses to use for
- * USB EHCI operations.
- *
- * @param index port number to start
- * @param hccr returns start address of EHCI HCCR registers
- * @param hcor returns start address of EHCI HCOR registers
- * @return 0 if ok, -1 on error (generally invalid port number)
- */
-int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
- struct fdt_usb *config;
- struct usb_ctlr *usbctlr;
- int ret;
-
- if (index >= port_count)
- return -1;
-
- config = &port[index];
- ehci_set_controller_priv(index, config, &tegra_ehci_ops);
-
- ret = usb_common_init(config, init);
- if (ret) {
- printf("tegrausb: Cannot init port %d\n", index);
- return ret;
- }
-
- config->initialized = 1;
-
- usbctlr = config->reg;
- *hccr = (struct ehci_hccr *)&usbctlr->cap_length;
- *hcor = (struct ehci_hcor *)&usbctlr->usb_cmd;
-
- return 0;
-}
-
-/*
- * Bring down the specified USB controller
- */
-int ehci_hcd_stop(int index)
-{
- usb_common_uninit(&port[index]);
-
- port[index].initialized = 0;
-
- return 0;
-}
-#endif /* !CONFIG_DM_USB */
-
-#ifdef CONFIG_DM_USB
static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
{
struct fdt_usb *priv = dev_get_priv(dev);
int ret;
- ret = fdt_decode_usb(gd->fdt_blob, dev->of_offset, priv);
+ ret = fdt_decode_usb(dev, priv);
if (ret)
return ret;
{ .compatible = "nvidia,tegra20-ehci", .data = USB_CTLR_T20 },
{ .compatible = "nvidia,tegra30-ehci", .data = USB_CTLR_T30 },
{ .compatible = "nvidia,tegra114-ehci", .data = USB_CTLR_T114 },
+ { .compatible = "nvidia,tegra210-ehci", .data = USB_CTLR_T210 },
{ }
};
.priv_auto_alloc_size = sizeof(struct fdt_usb),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
-#endif
projects / u-boot / blobdiff