#define HCS_N_PORTS(p) (((p) >> 0) & 0xf)
uint32_t cr_hccparams;
uint8_t cr_hcsp_portrt[8];
-} __attribute__ ((packed));
+} __attribute__ ((packed, aligned(4)));
struct ehci_hcor {
uint32_t or_usbcmd;
#define CMD_RESET (1 << 1) /* reset HC not bus */
#define CMD_RUN (1 << 0) /* start/stop HC */
uint32_t or_usbsts;
-#define STD_ASS (1 << 15)
+#define STS_ASS (1 << 15)
#define STS_HALT (1 << 12)
uint32_t or_usbintr;
+#define INTR_UE (1 << 0) /* USB interrupt enable */
+#define INTR_UEE (1 << 1) /* USB error interrupt enable */
+#define INTR_PCE (1 << 2) /* Port change detect enable */
+#define INTR_SEE (1 << 4) /* system error enable */
+#define INTR_AAE (1 << 5) /* Interrupt on async adavance enable */
uint32_t or_frindex;
uint32_t or_ctrldssegment;
uint32_t or_periodiclistbase;
uint32_t or_asynclistaddr;
- uint32_t _reserved_[9];
+ uint32_t _reserved_0_;
+ uint32_t or_burstsize;
+ uint32_t or_txfilltuning;
+#define TXFIFO_THRESH_MASK (0x3f << 16)
+#define TXFIFO_THRESH(p) ((p & 0x3f) << 16)
+ uint32_t _reserved_1_[6];
uint32_t or_configflag;
#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
+#define PORTSC_PSPD(x) (((x) >> 26) & 0x3)
+#define PORTSC_PSPD_FS 0x0
+#define PORTSC_PSPD_LS 0x1
+#define PORTSC_PSPD_HS 0x2
uint32_t or_systune;
-} __attribute__ ((packed));
+} __attribute__ ((packed, aligned(4)));
#define USBMODE 0x68 /* USB Device mode */
#define USBMODE_SDIS (1 << 3) /* Stream disable */
/* Queue Element Transfer Descriptor (qTD). */
struct qTD {
- uint32_t qt_next;
+ /* this part defined by EHCI spec */
+ uint32_t qt_next; /* see EHCI 3.5.1 */
#define QT_NEXT_TERMINATE 1
- uint32_t qt_altnext;
- uint32_t qt_token;
- uint32_t qt_buffer[5];
+ uint32_t qt_altnext; /* see EHCI 3.5.2 */
+ uint32_t qt_token; /* see EHCI 3.5.3 */
+#define QT_TOKEN_DT(x) (((x) & 0x1) << 31) /* Data Toggle */
+#define QT_TOKEN_GET_DT(x) (((x) >> 31) & 0x1)
+#define QT_TOKEN_TOTALBYTES(x) (((x) & 0x7fff) << 16) /* Total Bytes to Transfer */
+#define QT_TOKEN_GET_TOTALBYTES(x) (((x) >> 16) & 0x7fff)
+#define QT_TOKEN_IOC(x) (((x) & 0x1) << 15) /* Interrupt On Complete */
+#define QT_TOKEN_CPAGE(x) (((x) & 0x7) << 12) /* Current Page */
+#define QT_TOKEN_CERR(x) (((x) & 0x3) << 10) /* Error Counter */
+#define QT_TOKEN_PID(x) (((x) & 0x3) << 8) /* PID Code */
+#define QT_TOKEN_PID_OUT 0x0
+#define QT_TOKEN_PID_IN 0x1
+#define QT_TOKEN_PID_SETUP 0x2
+#define QT_TOKEN_STATUS(x) (((x) & 0xff) << 0) /* Status */
+#define QT_TOKEN_GET_STATUS(x) (((x) >> 0) & 0xff)
+#define QT_TOKEN_STATUS_ACTIVE 0x80
+#define QT_TOKEN_STATUS_HALTED 0x40
+#define QT_TOKEN_STATUS_DATBUFERR 0x20
+#define QT_TOKEN_STATUS_BABBLEDET 0x10
+#define QT_TOKEN_STATUS_XACTERR 0x08
+#define QT_TOKEN_STATUS_MISSEDUFRAME 0x04
+#define QT_TOKEN_STATUS_SPLITXSTATE 0x02
+#define QT_TOKEN_STATUS_PERR 0x01
+#define QT_BUFFER_CNT 5
+ uint32_t qt_buffer[QT_BUFFER_CNT]; /* see EHCI 3.5.4 */
+ uint32_t qt_buffer_hi[QT_BUFFER_CNT]; /* Appendix B */
+ /* pad struct for 32 byte alignment */
+ uint32_t unused[3];
};
+#define EHCI_PAGE_SIZE 4096
+
/* Queue Head (QH). */
struct QH {
uint32_t qh_link;
#define QH_LINK_TYPE_SITD 4
#define QH_LINK_TYPE_FSTN 6
uint32_t qh_endpt1;
+#define QH_ENDPT1_RL(x) (((x) & 0xf) << 28) /* NAK Count Reload */
+#define QH_ENDPT1_C(x) (((x) & 0x1) << 27) /* Control Endpoint Flag */
+#define QH_ENDPT1_MAXPKTLEN(x) (((x) & 0x7ff) << 16) /* Maximum Packet Length */
+#define QH_ENDPT1_H(x) (((x) & 0x1) << 15) /* Head of Reclamation List Flag */
+#define QH_ENDPT1_DTC(x) (((x) & 0x1) << 14) /* Data Toggle Control */
+#define QH_ENDPT1_DTC_IGNORE_QTD_TD 0x0
+#define QH_ENDPT1_DTC_DT_FROM_QTD 0x1
+#define QH_ENDPT1_EPS(x) (((x) & 0x3) << 12) /* Endpoint Speed */
+#define QH_ENDPT1_EPS_FS 0x0
+#define QH_ENDPT1_EPS_LS 0x1
+#define QH_ENDPT1_EPS_HS 0x2
+#define QH_ENDPT1_ENDPT(x) (((x) & 0xf) << 8) /* Endpoint Number */
+#define QH_ENDPT1_I(x) (((x) & 0x1) << 7) /* Inactivate on Next Transaction */
+#define QH_ENDPT1_DEVADDR(x) (((x) & 0x7f) << 0) /* Device Address */
uint32_t qh_endpt2;
+#define QH_ENDPT2_MULT(x) (((x) & 0x3) << 30) /* High-Bandwidth Pipe Multiplier */
+#define QH_ENDPT2_PORTNUM(x) (((x) & 0x7f) << 23) /* Port Number */
+#define QH_ENDPT2_HUBADDR(x) (((x) & 0x7f) << 16) /* Hub Address */
+#define QH_ENDPT2_UFCMASK(x) (((x) & 0xff) << 8) /* Split Completion Mask */
+#define QH_ENDPT2_UFSMASK(x) (((x) & 0xff) << 0) /* Interrupt Schedule Mask */
uint32_t qh_curtd;
struct qTD qh_overlay;
/*
};
/* Low level init functions */
-int ehci_hcd_init(void);
-int ehci_hcd_stop(void);
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor);
+int ehci_hcd_stop(int index);
#endif /* USB_EHCI_H */
projects / u-boot / blobdiff