*
* Copyright (C) 2012 Atmel Corporation
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
lcdc_writel(®s->lcdc_lcdcfg1, value);
- value = LCDC_LCDCFG2_VBPW(panel_info.vl_lower_margin);
- value |= LCDC_LCDCFG2_VFPW(panel_info.vl_upper_margin - 1);
+ value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin);
+ value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1);
lcdc_writel(®s->lcdc_lcdcfg2, value);
- value = LCDC_LCDCFG3_HBPW(panel_info.vl_right_margin - 1);
- value |= LCDC_LCDCFG3_HFPW(panel_info.vl_left_margin - 1);
+ value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1);
+ value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1);
lcdc_writel(®s->lcdc_lcdcfg3, value);
/* Display size */
| LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
desc->next = (u32)desc;
+ /* Flush the DMA descriptor if we enabled dcache */
+ flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
+
lcdc_writel(®s->lcdc_baseaddr, desc->address);
lcdc_writel(®s->lcdc_basectrl, desc->control);
lcdc_writel(®s->lcdc_basenext, desc->next);
lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_PWMEN);
while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))
udelay(1);
+
+ /* Enable flushing if we enabled dcache */
+ lcd_set_flush_dcache(1);
}