]> git.sur5r.net Git - u-boot/blobdiff - drivers/video/atmel_hlcdfb.c
video: ipu: fix out of bounds access
[u-boot] / drivers / video / atmel_hlcdfb.c
index bb4d7d8c1471ad9ca79b203ad4cc7cc03c673c01..960b474b76b863aa9cc59c9c8158631e88860c48 100644 (file)
 #include <lcd.h>
 #include <atmel_hlcdc.h>
 
+#if defined(CONFIG_LCD_LOGO)
+#include <bmp_logo.h>
+#endif
+
 /* configurable parameters */
 #define ATMEL_LCDC_CVAL_DEFAULT                0xc8
 #define ATMEL_LCDC_DMA_BURST_LEN       8
@@ -37,6 +41,15 @@ void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
                panel_info.mmio + ATMEL_LCDC_LUT(regno));
 }
 
+ushort *configuration_get_cmap(void)
+{
+#if defined(CONFIG_LCD_LOGO)
+       return bmp_logo_palette;
+#else
+       return NULL;
+#endif
+}
+
 void lcd_ctrl_init(void *lcdbase)
 {
        unsigned long value;
@@ -149,6 +162,10 @@ void lcd_ctrl_init(void *lcdbase)
                lcdc_writel(&regs->lcdc_basecfg1,
                        LCDC_BASECFG1_RGBMODE_16BPP_RGB_565);
                break;
+       case 32:
+               lcdc_writel(&regs->lcdc_basecfg1,
+                       LCDC_BASECFG1_RGBMODE_24BPP_RGB_888);
+               break;
        default:
                BUG();
                break;
@@ -171,6 +188,9 @@ void lcd_ctrl_init(void *lcdbase)
                        | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
        desc->next = (u32)desc;
 
+       /* Flush the DMA descriptor if we enabled dcache */
+       flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
+
        lcdc_writel(&regs->lcdc_baseaddr, desc->address);
        lcdc_writel(&regs->lcdc_basectrl, desc->control);
        lcdc_writel(&regs->lcdc_basenext, desc->next);
@@ -194,4 +214,7 @@ void lcd_ctrl_init(void *lcdbase)
        lcdc_writel(&regs->lcdc_lcden, value | LCDC_LCDEN_PWMEN);
        while (!(lcdc_readl(&regs->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))
                udelay(1);
+
+       /* Enable flushing if we enabled dcache */
+       lcd_set_flush_dcache(1);
 }