/* ported from ctfb.c (linux kernel):
- * Created in Jan - July 2000 by Thomas Höhenleitner <th@visuelle-maschinen.de>
+ * Created in Jan - July 2000 by Thomas Höhenleitner <th@visuelle-maschinen.de>
*
* Ported to U-Boot:
* (C) Copyright 2002 Denis Peter, MPL AG Switzerland
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <video_fb.h>
#include "videomodes.h"
-#ifdef CONFIG_VIDEO_CT69000
-
/* debug */
#undef VGA_DEBUG
#undef VGA_DUMP_REG
#ifdef VGA_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
+#undef _DEBUG
+#define _DEBUG 1
#else
-#define PRINTF(fmt,args...)
+#undef _DEBUG
+#define _DEBUG 0
#endif
/* Macros */
static const struct ctfb_chips_properties chips[] = {
{PCI_DEVICE_ID_CT_69000, 0x200000, 1, 4, -2, 3, 257, 100, 220},
-#ifdef CONFIG_USE_CPCIDVI
- {PCI_DEVICE_ID_CT_69030, 0x400000, 1, 4, -2, 3, 257, 100, 220},
-#endif
{PCI_DEVICE_ID_CT_65555, 0x100000, 16, 4, 0, 1, 255, 48, 220}, /* NOT TESTED */
{0, 0, 0, 0, 0, 0, 0, 0, 0} /* Terminator */
};
/* that is the hardware < 69000 we have to manage
+---------+ +-------------------+ +----------------------+ +--+
- | REFCLK |__|NTSC Divisor Select|__|FVCO Reference Divisor|__|÷N|__
- | 14.3MHz | |(NTSCDS) (÷1, ÷5) | |Select (RDS) (÷1, ÷4) | | | |
+ | REFCLK |__|NTSC Divisor Select|__|FVCO Reference Divisor|__|÷N|__
+ | 14.3MHz | |(NTSCDS) (÷1, ÷5) | |Select (RDS) (÷1, ÷4) | | | |
+---------+ +-------------------+ +----------------------+ +--+ |
___________________________________________________________________|
|
| fvco fout
| +--------+ +------------+ +-----+ +-------------------+ +----+
+-| Phase |__|Charge Pump |__| VCO |_____|Post Divisor (PD) |___|CLK |--->
- +-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | |
+ +-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | |
| +--------+ +------------+ +-----+ | +-------------------+ +----+
| |
| +--+ +---------------+ |
- |____|÷M|___|VCO Loop Divide|__________|
- | | |(VLD)(÷4, ÷16) |
+ |____|÷M|___|VCO Loop Divide|__________|
+ | | |(VLD)(÷4, ÷16) |
+--+ +---------------+
****************************************************************************
that is the hardware >= 69000 we have to manage
+---------+ +--+
- | REFCLK |__|÷N|__
+ | REFCLK |__|÷N|__
| 14.3MHz | | | |
+---------+ +--+ |
__________________|
| fvco fout
| +--------+ +------------+ +-----+ +-------------------+ +----+
+-| Phase |__|Charge Pump |__| VCO |_____|Post Divisor (PD) |___|CLK |--->
- +-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | |
+ +-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | |
| +--------+ +------------+ +-----+ | +-------------------+ +----+
| |
| +--+ +---------------+ |
- |____|÷M|___|VCO Loop Divide|__________|
- | | |(VLD)(÷1, ÷4) |
+ |____|÷M|___|VCO Loop Divide|__________|
+ | | |(VLD)(÷1, ÷4) |
+--+ +---------------+
}
m += param->mn_diff;
n += param->mn_diff;
- PRINTF ("VCO %d, pd %d, m %d n %d vld %d \n", fvco, pd, m, n, vld);
+ debug("VCO %d, pd %d, m %d n %d vld %d\n", fvco, pd, m, n, vld);
xr_cb = ((0x7 & PD) << 4) | (vld == param->vld_set ? 0x04 : 0);
/* All four of the registers used for dot clock 2 (XRC8 - XRCB) must be
* written, and in order from XRC8 to XRCB, before the hardware will
ctWrite_i (CT_XR_O, 0xca, 0); /* because of a hw bug I guess, but we write */
ctWrite_i (CT_XR_O, 0xcb, xr_cb); /* 0 to it for savety */
new_pixclock = ReadPixClckFromXrRegsBack (param);
- PRINTF ("pixelclock.set = %d, pixelclock.real = %d \n",
+ debug("pixelclock.set = %d, pixelclock.real = %d\n",
pixelclock, new_pixclock);
}
#endif
-#ifdef CONFIG_VIDEO_HW_CURSOR
-/***************************************************************
- * Set Hardware Cursor in Pixel
- */
-void
-video_set_hw_cursor (int x, int y)
-{
- int sig_x = 0, sig_y = 0;
- if (x < 0) {
- x *= -1;
- sig_x = 1;
- }
- if (y < 0) {
- y *= -1;
- sig_y = 1;
- }
- ctWrite_i (CT_XR_O, 0xa4, x & 0xff);
- ctWrite_i (CT_XR_O, 0xa5, (x >> 8) & 0x7);
- ctWrite_i (CT_XR_O, 0xa6, y & 0xff);
- ctWrite_i (CT_XR_O, 0xa7, (y >> 8) & 0x7);
-}
-
-/***************************************************************
- * Init Hardware Cursor. To know the size of the Cursor,
- * we have to know the Font size.
- */
-void
-video_init_hw_cursor (int font_width, int font_height)
-{
- unsigned char xr_80;
- unsigned long *curs, pattern;
- int i;
- int cursor_start;
- GraphicDevice *pGD = (GraphicDevice *) & ctfb;
-
- cursor_start = pGD->dprBase;
- xr_80 = ctRead_i (CT_XR_O, 0x80);
- /* set start address */
- ctWrite_i (CT_XR_O, 0xa2, (cursor_start >> 8) & 0xf0);
- ctWrite_i (CT_XR_O, 0xa3, (cursor_start >> 16) & 0x3f);
- /* set cursor shape */
- curs = (unsigned long *) cursor_start;
- i = 0;
- while (i < 0x400) {
- curs[i++] = 0xffffffff; /* AND mask */
- curs[i++] = 0xffffffff; /* AND mask */
- curs[i++] = 0; /* XOR mask */
- curs[i++] = 0; /* XOR mask */
- /* Transparent */
- }
- pattern = 0xffffffff >> font_width;
- i = 0;
- while (i < (font_height * 2)) {
- curs[i++] = pattern; /* AND mask */
- curs[i++] = pattern; /* AND mask */
- curs[i++] = 0; /* XOR mask */
- curs[i++] = 0; /* XOR mask */
- /* Cursor Color 0 */
- }
- /* set blink rate */
- ctWrite_i (CT_FP_O, 0x19, 0xf);
-
- /* set cursors colors */
- xr_80 = ctRead_i (CT_XR_O, 0x80);
- xr_80 |= 0x1; /* alternate palette select */
- ctWrite_i (CT_XR_O, 0x80, xr_80);
- video_set_lut (4, CONSOLE_FG_COL, CONSOLE_FG_COL, CONSOLE_FG_COL);
- /* position 4 is color 0 cursor 0 */
- xr_80 &= 0xfe; /* normal palette select */
- ctWrite_i (CT_XR_O, 0x80, xr_80);
- /* cursor enable */
- ctWrite_i (CT_XR_O, 0xa0, 0x91);
- xr_80 |= 0x10; /* enable hwcursor */
- ctWrite_i (CT_XR_O, 0x80, xr_80);
- video_set_hw_cursor (0, 0);
-}
-#endif /* CONFIG_VIDEO_HW_CURSOR */
-
/***************************************************************
* Wait for BitBlt ready
*/
*/
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000},
-#ifdef CONFIG_USE_CPCIDVI
- {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030},
-#endif
{}
};
pGD->gdfIndex = GDF_24BIT_888RGB;
break;
}
- pGD->isaBase = CFG_ISA_IO_BASE_ADDRESS;
+ pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS;
pGD->pciBase = pci_mem_base;
pGD->frameAdrs = pci_mem_base;
pGD->memSize = chips_param->max_mem;
pGD->dprBase &= 0xfffff000;
pGD->dprBase += 0x00001000;
}
- PRINTF ("Cursor Start %x Pattern Start %x\n", pGD->dprBase,
+ debug("Cursor Start %x Pattern Start %x\n", pGD->dprBase,
PATTERN_ADR);
pGD->vprBase = pci_mem_base; /* Dummy */
pGD->cprBase = pci_mem_base; /* Dummy */
/* set up Hardware */
-#ifdef CONFIG_USE_CPCIDVI
- if (device_id == PCI_DEVICE_ID_CT_69030) {
- ctWrite (CT_MSR_W_O, 0x0b);
- ctWrite (0x3cd, 0x13);
- ctWrite_i (CT_FP_O, 0x02, 0x00);
- ctWrite_i (CT_FP_O, 0x05, 0x00);
- ctWrite_i (CT_FP_O, 0x06, 0x00);
- ctWrite (0x3c2, 0x0b);
- ctWrite_i (CT_FP_O, 0x02, 0x10);
- ctWrite_i (CT_FP_O, 0x01, 0x09);
- } else {
- ctWrite (CT_MSR_W_O, 0x01);
- }
-#else
ctWrite (CT_MSR_W_O, 0x01);
-#endif
/* set the extended Registers */
ctLoadRegs (CT_XR_O, xreg);
out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x); /* start the BITBlt */
video_wait_bitblt (pGD->pciBase + BR04_o);
}
-
-#endif /* CONFIG_CT69000 */
-
#endif /* CONFIG_VIDEO */
projects / u-boot / blobdiff