video: fsl_dcu_fb: Enable pixel clock after initialization

[u-boot] / drivers / video / fsl_dcu_fb.c

diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c
index 7f03290b746b11fe8de49525f149fd96b0dddf69..c6ed3c40bcedda778fa9821f76eafca839f583f9 100644 (file)
--- a/drivers/video/fsl_dcu_fb.c
+++ b/drivers/video/fsl_dcu_fb.c
@@ -41,7 +41,7 @@
 #define DCU_VSYN_PARA_BP(x)            ((x) << 22)
 #define DCU_VSYN_PARA_PW(x)            ((x) << 11)
 #define DCU_VSYN_PARA_FP(x)            (x)
-#define DCU_SYN_POL_INV_PXCK_FALL      (0 << 6)
+#define DCU_SYN_POL_INV_PXCK_FALL      (1 << 6)
 #define DCU_SYN_POL_NEG_REMAIN         (0 << 5)
 #define DCU_SYN_POL_INV_VS_LOW         (1 << 1)
 #define DCU_SYN_POL_INV_HS_LOW         (1)
@@ -191,8 +191,6 @@ static void reset_total_layers(void)
                dcu_write32(&regs->ctrldescl[i][9], 0);
                dcu_write32(&regs->ctrldescl[i][10], 0);
        }
-
-       dcu_write32(&regs->update_mode, DCU_UPDATE_MODE_READREG);
 }
 
 static int layer_ctrldesc_init(int index, u32 pixel_format)
@@ -246,8 +244,6 @@ static int layer_ctrldesc_init(int index, u32 pixel_format)
        dcu_write32(&regs->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0));
        dcu_write32(&regs->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0));
 
-       dcu_write32(&regs->update_mode, DCU_UPDATE_MODE_READREG);
-
        return 0;
 }
 
@@ -273,8 +269,6 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres,
        memset(info.screen_base, 0, info.screen_size);
 
        reset_total_layers();
-       div = dcu_set_pixel_clock(info.var.pixclock);
-       dcu_write32(&regs->div_ratio, (div - 1));
 
        dcu_write32(&regs->disp_size,
                    DCU_DISP_SIZE_DELTA_Y(info.var.yres) |
@@ -313,6 +307,11 @@ int fsl_dcu_init(unsigned int xres, unsigned int yres,
 
        layer_ctrldesc_init(0, pixel_format);
 
+       div = dcu_set_pixel_clock(info.var.pixclock);
+       dcu_write32(&regs->div_ratio, (div - 1));
+
+       dcu_write32(&regs->update_mode, DCU_UPDATE_MODE_READREG);
+
        return 0;
 }