ARM: fix u-boot.lds for -ffunction-sections/-fdata-sections

[u-boot] / drivers / video / ipu_common.c

diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c
index e43a6ecde7a20e78333fe5cbd7540bfa3d38cb33..0f2d113a6f18d0e2ecc32eb00b2f13ad6d7454a1 100644 (file)
--- a/drivers/video/ipu_common.c
+++ b/drivers/video/ipu_common.c
@@ -163,13 +163,13 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
 
 static int clk_ipu_enable(struct clk *clk)
 {
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
        u32 reg;
 
        reg = __raw_readl(clk->enable_reg);
        reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift;
        __raw_writel(reg, clk->enable_reg);
 
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
        /* Handshake with IPU when certain clock rates are changed. */
        reg = __raw_readl(&mxc_ccm->ccdr);
        reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
@@ -185,13 +185,13 @@ static int clk_ipu_enable(struct clk *clk)
 
 static void clk_ipu_disable(struct clk *clk)
 {
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
        u32 reg;
 
        reg = __raw_readl(clk->enable_reg);
        reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift);
        __raw_writel(reg, clk->enable_reg);
 
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
        /*
         * No handshake with IPU whe dividers are changed
         * as its not enabled.
@@ -211,16 +211,29 @@ static void clk_ipu_disable(struct clk *clk)
 static struct clk ipu_clk = {
        .name = "ipu_clk",
        .rate = CONFIG_IPUV3_CLK,
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
        .enable_reg = (u32 *)(CCM_BASE_ADDR +
                offsetof(struct mxc_ccm_reg, CCGR5)),
-       .enable_shift = MXC_CCM_CCGR5_CG5_OFFSET,
+       .enable_shift = MXC_CCM_CCGR5_IPU_OFFSET,
+#else
+       .enable_reg = (u32 *)(CCM_BASE_ADDR +
+               offsetof(struct mxc_ccm_reg, CCGR3)),
+       .enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET,
+#endif
        .enable = clk_ipu_enable,
        .disable = clk_ipu_disable,
        .usecount = 0,
 };
 
+static struct clk ldb_clk = {
+       .name = "ldb_clk",
+       .rate = 65000000,
+       .usecount = 0,
+};
+
 /* Globals */
 struct clk *g_ipu_clk;
+struct clk *g_ldb_clk;
 unsigned char g_ipu_clk_enabled;
 struct clk *g_di_clk[2];
 struct clk *g_pixel_clk[2];
@@ -343,7 +356,7 @@ static int ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent)
 
        if (parent == g_ipu_clk)
                di_gen &= ~DI_GEN_DI_CLK_EXT;
-       else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_di_clk[clk->id])
+       else if (!IS_ERR(g_di_clk[clk->id]) && parent == g_ldb_clk)
                di_gen |= DI_GEN_DI_CLK_EXT;
        else
                return -EINVAL;
@@ -429,7 +442,8 @@ int ipu_probe(void)
 
        g_ipu_clk = &ipu_clk;
        debug("ipu_clk = %u\n", clk_get_rate(g_ipu_clk));
-
+       g_ldb_clk = &ldb_clk;
+       debug("ldb_clk = %u\n", clk_get_rate(g_ldb_clk));
        ipu_reset();
 
        clk_set_parent(g_pixel_clk[0], g_ipu_clk);