rockchip: board: puma_rk3399: add support for serial# and cpuid# via efuses

[u-boot] / drivers / video / ipu_common.c

diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c
index ad4af5283a97d2985f39443c0e5053000fb7bca2..f8d4488fcef4a94483de9cd66920e23b1825d78a 100644 (file)
--- a/drivers/video/ipu_common.c
+++ b/drivers/video/ipu_common.c
@@ -8,23 +8,7 @@
  *
  * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /* #define DEBUG */
@@ -32,9 +16,10 @@
 #include <linux/types.h>
 #include <linux/err.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
+#include <div64.h>
 #include "ipu.h"
 #include "ipu_regs.h"
 
@@ -226,9 +211,13 @@ static struct clk ipu_clk = {
        .usecount = 0,
 };
 
+#if !defined CONFIG_SYS_LDB_CLOCK
+#define CONFIG_SYS_LDB_CLOCK 65000000
+#endif
+
 static struct clk ldb_clk = {
        .name = "ldb_clk",
-       .rate = 65000000,
+       .rate = CONFIG_SYS_LDB_CLOCK,
        .usecount = 0,
 };
 
@@ -287,50 +276,86 @@ static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum,
 
 static void ipu_pixel_clk_recalc(struct clk *clk)
 {
-       u32 div = __raw_readl(DI_BS_CLKGEN0(clk->id));
-       if (div == 0)
-               clk->rate = 0;
-       else
-               clk->rate = (clk->parent->rate * 16) / div;
+       u32 div;
+       u64 final_rate = (unsigned long long)clk->parent->rate * 16;
+
+       div = __raw_readl(DI_BS_CLKGEN0(clk->id));
+       debug("read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\n",
+             div, final_rate, clk->parent->rate);
+
+       clk->rate = 0;
+       if (div != 0) {
+               do_div(final_rate, div);
+               clk->rate = final_rate;
+       }
 }
 
 static unsigned long ipu_pixel_clk_round_rate(struct clk *clk,
        unsigned long rate)
 {
-       u32 div, div1;
-       u32 tmp;
+       u64 div, final_rate;
+       u32 remainder;
+       u64 parent_rate = (unsigned long long)clk->parent->rate * 16;
+
        /*
         * Calculate divider
         * Fractional part is 4 bits,
         * so simply multiply by 2^4 to get fractional part.
         */
-       tmp = (clk->parent->rate * 16);
-       div = tmp / rate;
-
+       div = parent_rate;
+       remainder = do_div(div, rate);
+       /* Round the divider value */
+       if (remainder > (rate / 2))
+               div++;
        if (div < 0x10)            /* Min DI disp clock divider is 1 */
                div = 0x10;
        if (div & ~0xFEF)
                div &= 0xFF8;
        else {
-               div1 = div & 0xFE0;
-               if ((tmp/div1 - tmp/div) < rate / 4)
-                       div = div1;
-               else
-                       div &= 0xFF8;
+               /* Round up divider if it gets us closer to desired pix clk */
+               if ((div & 0xC) == 0xC) {
+                       div += 0x10;
+                       div &= ~0xF;
+               }
        }
-       return (clk->parent->rate * 16) / div;
+       final_rate = parent_rate;
+       do_div(final_rate, div);
+
+       return final_rate;
 }
 
 static int ipu_pixel_clk_set_rate(struct clk *clk, unsigned long rate)
 {
-       u32 div = (clk->parent->rate * 16) / rate;
+       u64 div, parent_rate;
+       u32 remainder;
+
+       parent_rate = (unsigned long long)clk->parent->rate * 16;
+       div = parent_rate;
+       remainder = do_div(div, rate);
+       /* Round the divider value */
+       if (remainder > (rate / 2))
+               div++;
+
+       /* Round up divider if it gets us closer to desired pix clk */
+       if ((div & 0xC) == 0xC) {
+               div += 0x10;
+               div &= ~0xF;
+       }
+       if (div > 0x1000)
+               debug("Overflow, DI_BS_CLKGEN0 div:0x%x\n", (u32)div);
 
        __raw_writel(div, DI_BS_CLKGEN0(clk->id));
 
-       /* Setup pixel clock timing */
+       /*
+        * Setup pixel clock timing
+        * Down time is half of period
+        */
        __raw_writel((div / 16) << 16, DI_BS_CLKGEN1(clk->id));
 
-       clk->rate = (clk->parent->rate * 16) / div;
+       do_div(parent_rate, div);
+
+       clk->rate = parent_rate;
+
        return 0;
 }
 
@@ -395,7 +420,7 @@ static struct clk pixel_clk[] = {
 /*
  * This function resets IPU
  */
-void ipu_reset(void)
+static void ipu_reset(void)
 {
        u32 *reg;
        u32 value;
@@ -1210,3 +1235,11 @@ ipu_color_space_t format_to_colorspace(uint32_t fmt)
        }
        return RGB;
 }
+
+/* should be removed when clk framework is availiable */
+int ipu_set_ldb_clock(int rate)
+{
+       ldb_clk.rate = rate;
+
+       return 0;
+}