mtd: nand: mxs_nand: add minimal ECC support

[u-boot] / drivers / video / ipu_regs.h

diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h
index 982e25250970c45db57eeec2f82f55d70dc3e182..deb44002d75359293638f53966ca0f215fd357e1 100644 (file)
--- a/drivers/video/ipu_regs.h
+++ b/drivers/video/ipu_regs.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Porting to u-boot:
  *
@@ -7,24 +8,6 @@
  * Linux IPU driver for MX51:
  *
  * (C) Copyright 2005-2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
  */
 
 #ifndef __IPU_REGS_INCLUDED__
@@ -187,7 +170,7 @@ struct ipu_cm {
        u32 gpr;
        u32 reserved0[26];
        u32 ch_db_mode_sel[2];
-       u32 reserved1[16];
+       u32 reserved1[4];
        u32 alt_ch_db_mode_sel[2];
        u32 reserved2[2];
        u32 ch_trb_mode_sel[2];
@@ -204,7 +187,7 @@ struct ipu_idmac {
        u32 sub_addr[5];
        u32 bndm_en[2];
        u32 sc_cord[2];
-       u32 reserved[45];
+       u32 reserved[44];
        u32 ch_busy[2];
 };
 
@@ -329,9 +312,12 @@ struct ipu_dmfc {
 
 #define IPU_STAT               ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \
                                IPU_STAT_REG_BASE))
+#define IPU_INT_STAT(n)                (&IPU_STAT->int_stat[(n) - 1])
 #define IPU_CHA_CUR_BUF(ch)    (&IPU_STAT->cur_buf[ch / 32])
 #define IPU_CHA_BUF0_RDY(ch)   (&IPU_STAT->ch_buf0_rdy[ch / 32])
 #define IPU_CHA_BUF1_RDY(ch)   (&IPU_STAT->ch_buf1_rdy[ch / 32])
+#define IPUIRQ_2_STATREG(irq)  (IPU_INT_STAT(1) + ((irq) / 32))
+#define IPUIRQ_2_MASK(irq)     (1UL << ((irq) & 0x1F))
 
 #define IPU_INT_CTRL(n)                (&IPU_CM_REG->int_ctrl[(n) - 1])
 
@@ -351,6 +337,7 @@ struct ipu_dmfc {
 #define DI_SW_GEN0(di, gen)    (&DI_REG(di)->sw_gen0[gen - 1])
 #define DI_SW_GEN1(di, gen)    (&DI_REG(di)->sw_gen1[gen - 1])
 #define DI_STP_REP(di, gen)    (&DI_REG(di)->stp_rep[(gen - 1) / 2])
+#define DI_STP_REP9(di)                (&DI_REG(di)->stp_rep9)
 #define DI_SYNC_AS_GEN(di)     (&DI_REG(di)->sync_as)
 #define DI_DW_GEN(di, gen)     (&DI_REG(di)->dw_gen[gen])
 #define DI_DW_SET(di, gen, set)        (&DI_REG(di)->dw_set[gen + 12 * set])