video: Name consoles by their number

[u-boot] / drivers / video / mxsfb.c

diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index c55cb44ffd64dcc23e395421d41e78270ed118e7..ddbb118d709e4a2521af801099cb80e15f484fff 100644 (file)
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -15,11 +15,14 @@
 #include <asm/errno.h>
 #include <asm/io.h>
 
+#include <asm/imx-common/dma.h>
+
 #include "videomodes.h"
 
 #define        PS2KHZ(ps)      (1000000000UL / (ps))
 
 static GraphicDevice panel;
+struct mxs_dma_desc desc;
 
 /**
  * mxsfb_system_setup() - Fine-tune LCDIF configuration
@@ -52,7 +55,7 @@ static void mxs_lcd_init(GraphicDevice *panel,
        uint8_t valid_data = 0;
 
        /* Kick in the LCDIF clock */
-       mxs_set_lcdclk(PS2KHZ(mode->pixclock));
+       mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock));
 
        /* Restart the LCDIF block */
        mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
@@ -128,6 +131,23 @@ static void mxs_lcd_init(GraphicDevice *panel,
        writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
 }
 
+void lcdif_power_down(void)
+{
+       struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+       int timeout = 1000000;
+
+       writel(panel.frameAdrs, &regs->hw_lcdif_cur_buf_reg);
+       writel(panel.frameAdrs, &regs->hw_lcdif_next_buf_reg);
+       writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr);
+       while (--timeout) {
+               if (readl(&regs->hw_lcdif_ctrl1_reg) &
+                   LCDIF_CTRL1_VSYNC_EDGE_IRQ)
+                       break;
+               udelay(1);
+       }
+       mxs_reset_block((struct mxs_register_32 *)&regs->hw_lcdif_ctrl_reg);
+}
+
 void *video_hw_init(void)
 {
        int bpp = -1;
@@ -194,5 +214,28 @@ void *video_hw_init(void)
        /* Start framebuffer */
        mxs_lcd_init(&panel, &mode, bpp);
 
+#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
+       /*
+        * If the LCD runs in system mode, the LCD refresh has to be triggered
+        * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
+        * having to set this bit manually after every single change in the
+        * framebuffer memory, we set up specially crafted circular DMA, which
+        * sets the RUN bit, then waits until it gets cleared and repeats this
+        * infinitelly. This way, we get smooth continuous updates of the LCD.
+        */
+       struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+
+       memset(&desc, 0, sizeof(struct mxs_dma_desc));
+       desc.address = (dma_addr_t)&desc;
+       desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
+                       MXS_DMA_DESC_WAIT4END |
+                       (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
+       desc.cmd.pio_words[0] = readl(&regs->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
+       desc.cmd.next = (uint32_t)&desc.cmd;
+
+       /* Execute the DMA chain. */
+       mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
+#endif
+
        return (void *)&panel;
 }