+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2011 The Chromium OS Authors.
- * SPDX-License-Identifier: GPL-2.0+
*/
-#define DEBUG
+
#include <common.h>
#include <dm.h>
#include <fdtdec.h>
+#include <panel.h>
+#include <pwm.h>
#include <video.h>
#include <asm/system.h>
#include <asm/gpio.h>
DECLARE_GLOBAL_DATA_PTR;
-/* These are the stages we go throuh in enabling the LCD */
-enum stage_t {
- STAGE_START,
- STAGE_PANEL_VDD,
- STAGE_LVDS,
- STAGE_BACKLIGHT_VDD,
- STAGE_PWM,
- STAGE_BACKLIGHT_EN,
- STAGE_DONE,
-};
-
-static enum stage_t stage; /* Current stage we are at */
-static unsigned long timer_next; /* Time we can move onto next stage */
-
/* Information about the display controller */
struct tegra_lcd_priv {
int width; /* width in pixels */
int height; /* height in pixels */
- int bpp; /* number of bits per pixel */
-
- /*
- * log2 of number of bpp, in general, unless it bpp is 24 in which
- * case this field holds 24 also! This is a U-Boot thing.
- */
- int log2_bpp;
+ enum video_log2_bpp log2_bpp; /* colour depth */
+ struct display_timing timing;
+ struct udevice *panel;
struct disp_ctlr *disp; /* Display controller to use */
fdt_addr_t frame_buffer; /* Address of frame buffer */
unsigned pixel_clock; /* Pixel clock in Hz */
- uint horiz_timing[FDT_LCD_TIMING_COUNT]; /* Horizontal timing */
- uint vert_timing[FDT_LCD_TIMING_COUNT]; /* Vertical timing */
- int panel_node; /* node offset of panel information */
- int pwm_channel; /* PWM channel to use for backlight */
- enum lcd_cache_t cache_type;
-
- struct gpio_desc backlight_en; /* GPIO for backlight enable */
- struct gpio_desc lvds_shutdown; /* GPIO for lvds shutdown */
- struct gpio_desc backlight_vdd; /* GPIO for backlight vdd */
- struct gpio_desc panel_vdd; /* GPIO for panel vdd */
- /*
- * Panel required timings
- * Timing 1: delay between panel_vdd-rise and data-rise
- * Timing 2: delay between data-rise and backlight_vdd-rise
- * Timing 3: delay between backlight_vdd and pwm-rise
- * Timing 4: delay between pwm-rise and backlight_en-rise
- */
- uint panel_timings[FDT_LCD_TIMINGS];
};
enum {
writel(val, &dc->cmd.state_ctrl);
}
-static void write_pair(struct tegra_lcd_priv *priv, int item, u32 *reg)
-{
- writel(priv->horiz_timing[item] |
- (priv->vert_timing[item] << 16), reg);
-}
-
static int update_display_mode(struct dc_disp_reg *disp,
struct tegra_lcd_priv *priv)
{
+ struct display_timing *dt = &priv->timing;
unsigned long val;
unsigned long rate;
unsigned long div;
writel(0x0, &disp->disp_timing_opt);
- write_pair(priv, FDT_LCD_TIMING_REF_TO_SYNC, &disp->ref_to_sync);
- write_pair(priv, FDT_LCD_TIMING_SYNC_WIDTH, &disp->sync_width);
- write_pair(priv, FDT_LCD_TIMING_BACK_PORCH, &disp->back_porch);
- write_pair(priv, FDT_LCD_TIMING_FRONT_PORCH, &disp->front_porch);
- writel(priv->width | (priv->height << 16), &disp->disp_active);
+ writel(1 | 1 << 16, &disp->ref_to_sync);
+ writel(dt->hsync_len.typ | dt->vsync_len.typ << 16, &disp->sync_width);
+ writel(dt->hback_porch.typ | dt->vback_porch.typ << 16,
+ &disp->back_porch);
+ writel((dt->hfront_porch.typ - 1) | (dt->vfront_porch.typ - 1) << 16,
+ &disp->front_porch);
+ writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active);
val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
win->stride = priv->width * (1 << priv->log2_bpp) / 8;
debug("%s: depth = %d\n", __func__, priv->log2_bpp);
switch (priv->log2_bpp) {
- case 5:
- case 24:
+ case VIDEO_BPP32:
win->fmt = COLOR_DEPTH_R8G8B8A8;
win->bpp = 32;
break;
- case 4:
+ case VIDEO_BPP16:
win->fmt = COLOR_DEPTH_B5G6R5;
win->bpp = 16;
break;
return 0;
}
-static void debug_timing(const char *name, unsigned int timing[])
-{
-#ifdef DEBUG
- int i;
-
- debug("%s timing: ", name);
- for (i = 0; i < FDT_LCD_TIMING_COUNT; i++)
- debug("%d ", timing[i]);
- debug("\n");
-#endif
-}
-
-/**
- * Decode panel information from the fdt, according to a standard binding
- *
- * @param blob fdt blob
- * @param node offset of fdt node to read from
- * @param priv structure to store fdt config into
- * @return 0 if ok, -ve on error
- */
-static int tegra_decode_panel(const void *blob, int node,
- struct tegra_lcd_priv *priv)
-{
- int front, back, ref;
-
- priv->width = fdtdec_get_int(blob, node, "xres", -1);
- priv->height = fdtdec_get_int(blob, node, "yres", -1);
- priv->pixel_clock = fdtdec_get_int(blob, node, "clock", 0);
- if (!priv->pixel_clock || priv->width == -1 || priv->height == -1) {
- debug("%s: Pixel parameters missing\n", __func__);
- return -FDT_ERR_NOTFOUND;
- }
-
- back = fdtdec_get_int(blob, node, "left-margin", -1);
- front = fdtdec_get_int(blob, node, "right-margin", -1);
- ref = fdtdec_get_int(blob, node, "hsync-len", -1);
- if ((back | front | ref) == -1) {
- debug("%s: Horizontal parameters missing\n", __func__);
- return -FDT_ERR_NOTFOUND;
- }
-
- /* Use a ref-to-sync of 1 always, and take this from the front porch */
- priv->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
- priv->horiz_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
- priv->horiz_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
- priv->horiz_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
- priv->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC];
- debug_timing("horiz", priv->horiz_timing);
-
- back = fdtdec_get_int(blob, node, "upper-margin", -1);
- front = fdtdec_get_int(blob, node, "lower-margin", -1);
- ref = fdtdec_get_int(blob, node, "vsync-len", -1);
- if ((back | front | ref) == -1) {
- debug("%s: Vertical parameters missing\n", __func__);
- return -FDT_ERR_NOTFOUND;
- }
-
- priv->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
- priv->vert_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
- priv->vert_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
- priv->vert_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
- priv->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC];
- debug_timing("vert", priv->vert_timing);
-
- return 0;
-}
-
-/**
- * Decode the display controller information from the fdt.
- *
- * @param blob fdt blob
- * @param priv structure to store fdt priv into
- * @return 0 if ok, -ve on error
- */
-static int tegra_display_decode_config(const void *blob, int node,
- struct tegra_lcd_priv *priv)
-{
- int rgb;
- int bpp, bit;
-
- priv->disp = (struct disp_ctlr *)fdtdec_get_addr(blob, node, "reg");
- if (!priv->disp) {
- debug("%s: No display controller address\n", __func__);
- return -1;
- }
-
- rgb = fdt_subnode_offset(blob, node, "rgb");
-
- priv->panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
- if (priv->panel_node < 0) {
- debug("%s: Cannot find panel information\n", __func__);
- return -1;
- }
-
- if (tegra_decode_panel(blob, priv->panel_node, priv)) {
- debug("%s: Failed to decode panel information\n", __func__);
- return -1;
- }
-
- bpp = fdtdec_get_int(blob, priv->panel_node, "nvidia,bits-per-pixel",
- -1);
- bit = ffs(bpp) - 1;
- if (bpp == (1 << bit))
- priv->log2_bpp = bit;
- else
- priv->log2_bpp = bpp;
- if (bpp == -1) {
- debug("%s: Pixel bpp parameters missing\n", __func__);
- return -FDT_ERR_NOTFOUND;
- }
- priv->bpp = bpp;
-
- return 0;
-}
-
/**
* Register a new display based on device tree configuration.
*
- * The frame buffer can be positioned by U-Boot or overriden by the fdt.
+ * The frame buffer can be positioned by U-Boot or overridden by the fdt.
* You should pass in the U-Boot address here, and check the contents of
* struct tegra_lcd_priv to see what was actually chosen.
*
return 0;
}
-/**
- * Decode the panel information from the fdt.
- *
- * @param blob fdt blob
- * @param priv structure to store fdt config into
- * @return 0 if ok, -ve on error
- */
-static int fdt_decode_lcd(const void *blob, struct tegra_lcd_priv *priv)
+static int tegra_lcd_probe(struct udevice *dev)
{
- int display_node;
-
- display_node = priv->panel_node;
- if (display_node < 0) {
- debug("%s: No panel configuration available\n", __func__);
- return -1;
- }
+ struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct tegra_lcd_priv *priv = dev_get_priv(dev);
+ const void *blob = gd->fdt_blob;
+ int ret;
- priv->pwm_channel = pwm_request(blob, display_node, "nvidia,pwm");
- if (priv->pwm_channel < 0) {
- debug("%s: Unable to request PWM channel\n", __func__);
+ /* Initialize the Tegra display controller */
+ funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
+ if (tegra_display_probe(blob, priv, (void *)plat->base)) {
+ printf("%s: Failed to probe display driver\n", __func__);
return -1;
}
- priv->cache_type = fdtdec_get_int(blob, display_node,
- "nvidia,cache-type",
- FDT_LCD_CACHE_WRITE_BACK_FLUSH);
-
- /* These GPIOs are all optional */
- gpio_request_by_name_nodev(blob, display_node,
- "nvidia,backlight-enable-gpios", 0,
- &priv->backlight_en, GPIOD_IS_OUT);
- gpio_request_by_name_nodev(blob, display_node,
- "nvidia,lvds-shutdown-gpios", 0,
- &priv->lvds_shutdown, GPIOD_IS_OUT);
- gpio_request_by_name_nodev(blob, display_node,
- "nvidia,backlight-vdd-gpios", 0,
- &priv->backlight_vdd, GPIOD_IS_OUT);
- gpio_request_by_name_nodev(blob, display_node,
- "nvidia,panel-vdd-gpios", 0,
- &priv->panel_vdd, GPIOD_IS_OUT);
-
- return fdtdec_get_int_array(blob, display_node, "nvidia,panel-timings",
- priv->panel_timings, FDT_LCD_TIMINGS);
-}
-
-/**
- * Handle the next stage of device init
- */
-static int handle_stage(const void *blob, struct tegra_lcd_priv *priv)
-{
- debug("%s: stage %d\n", __func__, stage);
-
- /* do the things for this stage */
- switch (stage) {
- case STAGE_START:
- /*
- * It is possible that the FDT has requested that the LCD be
- * disabled. We currently don't support this. It would require
- * changes to U-Boot LCD subsystem to have LCD support
- * compiled in but not used. An easier option might be to
- * still have a frame buffer, but leave the backlight off and
- * remove all mention of lcd in the stdout environment
- * variable.
- */
-
- funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
- break;
- case STAGE_PANEL_VDD:
- if (dm_gpio_is_valid(&priv->panel_vdd))
- dm_gpio_set_value(&priv->panel_vdd, 1);
- break;
- case STAGE_LVDS:
- if (dm_gpio_is_valid(&priv->lvds_shutdown))
- dm_gpio_set_value(&priv->lvds_shutdown, 1);
- break;
- case STAGE_BACKLIGHT_VDD:
- if (dm_gpio_is_valid(&priv->backlight_vdd))
- dm_gpio_set_value(&priv->backlight_vdd, 1);
- break;
- case STAGE_PWM:
- /* Enable PWM at 15/16 high, 32768 Hz with divider 1 */
- pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
- pinmux_tristate_disable(PMUX_PINGRP_GPU);
+ pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
+ pinmux_tristate_disable(PMUX_PINGRP_GPU);
- pwm_enable(priv->pwm_channel, 32768, 0xdf, 1);
- break;
- case STAGE_BACKLIGHT_EN:
- if (dm_gpio_is_valid(&priv->backlight_en))
- dm_gpio_set_value(&priv->backlight_en, 1);
- break;
- case STAGE_DONE:
- break;
+ ret = panel_enable_backlight(priv->panel);
+ if (ret) {
+ debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);
+ return ret;
}
- /* set up timer for next stage */
- timer_next = timer_get_us();
- if (stage < FDT_LCD_TIMINGS)
- timer_next += priv->panel_timings[stage] * 1000;
+ mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size,
+ DCACHE_WRITETHROUGH);
- /* move to next stage */
- stage++;
- return 0;
-}
+ /* Enable flushing after LCD writes if requested */
+ video_set_flush_dcache(dev, true);
-/**
- * Perform the next stage of the LCD init if it is time to do so.
- *
- * LCD init can be time-consuming because of the number of delays we need
- * while waiting for the backlight power supply, etc. This function can
- * be called at various times during U-Boot operation to advance the
- * initialization of the LCD to the next stage if sufficient time has
- * passed since the last stage. It keeps track of what stage it is up to
- * and the time that it is permitted to move to the next stage.
- *
- * The final call should have wait=1 to complete the init.
- *
- * @param blob fdt blob containing LCD information
- * @param wait 1 to wait until all init is complete, and then return
- * 0 to return immediately, potentially doing nothing if it is
- * not yet time for the next init.
- */
-static int tegra_lcd_check_next_stage(const void *blob,
- struct tegra_lcd_priv *priv, int wait)
-{
- if (stage == STAGE_DONE)
- return 0;
-
- do {
- /* wait if we need to */
- debug("%s: stage %d\n", __func__, stage);
- if (stage != STAGE_START) {
- int delay = timer_next - timer_get_us();
-
- if (delay > 0) {
- if (wait)
- udelay(delay);
- else
- return 0;
- }
- }
-
- if (handle_stage(blob, priv))
- return -1;
- } while (wait && stage != STAGE_DONE);
- if (stage == STAGE_DONE)
- debug("%s: LCD init complete\n", __func__);
+ uc_priv->xsize = priv->width;
+ uc_priv->ysize = priv->height;
+ uc_priv->bpix = priv->log2_bpp;
+ debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer,
+ plat->size);
return 0;
}
-static int tegra_lcd_probe(struct udevice *dev)
+static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
{
- struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
- struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct tegra_lcd_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
- int type = DCACHE_OFF;
-
- if (tegra_display_decode_config(blob, dev->of_offset, priv))
- return -1;
+ struct display_timing *timing;
+ int node = dev_of_offset(dev);
+ int panel_node;
+ int rgb;
+ int ret;
- /* get panel details */
- if (fdt_decode_lcd(blob, priv)) {
- printf("No valid LCD information in device tree\n");
- return -1;
+ priv->disp = (struct disp_ctlr *)devfdt_get_addr(dev);
+ if (!priv->disp) {
+ debug("%s: No display controller address\n", __func__);
+ return -EINVAL;
}
- /* Initialize the Tegra display controller */
- if (tegra_display_probe(blob, priv, (void *)plat->base)) {
- printf("%s: Failed to probe display driver\n", __func__);
- return -1;
+ rgb = fdt_subnode_offset(blob, node, "rgb");
+ if (rgb < 0) {
+ debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n",
+ __func__, dev->name, rgb);
+ return -EINVAL;
}
- tegra_lcd_check_next_stage(blob, priv, 1);
-
- /* Set up the LCD caching as requested */
- if (priv->cache_type & FDT_LCD_CACHE_WRITE_THROUGH)
- type = DCACHE_WRITETHROUGH;
- else if (priv->cache_type & FDT_LCD_CACHE_WRITE_BACK)
- type = DCACHE_WRITEBACK;
- mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size, type);
-
- /* Enable flushing after LCD writes if requested */
- video_set_flush_dcache(dev, priv->cache_type & FDT_LCD_CACHE_FLUSH);
+ ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing);
+ if (ret) {
+ debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
+ __func__, dev->name, ret);
+ return -EINVAL;
+ }
+ timing = &priv->timing;
+ priv->width = timing->hactive.typ;
+ priv->height = timing->vactive.typ;
+ priv->pixel_clock = timing->pixelclock.typ;
+ priv->log2_bpp = VIDEO_BPP16;
- uc_priv->xsize = priv->width;
- uc_priv->ysize = priv->height;
- uc_priv->bpix = priv->log2_bpp;
- debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer,
- plat->size);
+ /*
+ * Sadly the panel phandle is in an rgb subnode so we cannot use
+ * uclass_get_device_by_phandle().
+ */
+ panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
+ if (panel_node < 0) {
+ debug("%s: Cannot find panel information\n", __func__);
+ return -EINVAL;
+ }
+ ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node,
+ &priv->panel);
+ if (ret) {
+ debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
+ dev->name, ret);
+ return ret;
+ }
return 0;
}
static int tegra_lcd_bind(struct udevice *dev)
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+ const void *blob = gd->fdt_blob;
+ int node = dev_of_offset(dev);
+ int rgb;
+
+ rgb = fdt_subnode_offset(blob, node, "rgb");
+ if ((rgb < 0) || !fdtdec_get_is_enabled(blob, rgb))
+ return -ENODEV;
plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
(1 << LCD_MAX_LOG2_BPP) / 8;
.ops = &tegra_lcd_ops,
.bind = tegra_lcd_bind,
.probe = tegra_lcd_probe,
+ .ofdata_to_platdata = tegra_lcd_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct tegra_lcd_priv),
};
projects / u-boot / blobdiff