reset: Rename CONFIG_SPL_RESET_SUPPORT to CONFIG_SPL_DM_RESET

[u-boot] / drivers / watchdog / imx_watchdog.c

diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c
index 1d18d4b269f8af94e4f8cae77bdc9a39b5524f8e..3f826d10eb918cb9970ece1ed1e8c7466cbc8500 100644 (file)
--- a/drivers/watchdog/imx_watchdog.c
+++ b/drivers/watchdog/imx_watchdog.c
@@ -8,19 +8,7 @@
 #include <asm/io.h>
 #include <watchdog.h>
 #include <asm/arch/imx-regs.h>
-
-struct watchdog_regs {
-       u16     wcr;    /* Control */
-       u16     wsr;    /* Service */
-       u16     wrsr;   /* Reset Status */
-};
-
-#define WCR_WDZST      0x01
-#define WCR_WDBG       0x02
-#define WCR_WDE                0x04    /* WDOG enable */
-#define WCR_WDT                0x08
-#define WCR_SRS                0x10
-#define SET_WCR_WT(x)  (x << 8)
+#include <fsl_wdog.h>
 
 #ifdef CONFIG_IMX_WATCHDOG
 void hw_watchdog_reset(void)
@@ -46,16 +34,17 @@ void hw_watchdog_init(void)
 #endif
        timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
        writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS |
-               SET_WCR_WT(timeout), &wdog->wcr);
+               WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr);
        hw_watchdog_reset();
 }
 #endif
 
-void reset_cpu(ulong addr)
+void __attribute__((weak)) reset_cpu(ulong addr)
 {
        struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
 
-       writew(WCR_WDE, &wdog->wcr);
+       clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE);
+
        writew(0x5555, &wdog->wsr);
        writew(0xaaaa, &wdog->wsr);     /* load minimum 1/2 second timeout */
        while (1) {