FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.

[u-boot] / examples / Makefile

diff --git a/examples/Makefile b/examples/Makefile
index 60a6f5ea56db319c3d23a74b53fa2ab9734af61d..66b354daaf67d82dd4893f59a7050f2158afa79d 100644 (file)
--- a/examples/Makefile
+++ b/examples/Makefile
@@ -69,6 +69,9 @@ ifeq ($(ARCH),sh)
 LOAD_ADDR = 0x8C000000
 endif
 
+ifeq ($(ARCH),sparc)
+LOAD_ADDR = 0x00000000 -L $(gcclibdir) -T sparc.lds
+endif
 
 include $(TOPDIR)/config.mk
 
@@ -77,9 +80,9 @@ SREC  = hello_world.srec
 BIN    = hello_world.bin
 
 ifeq ($(CPU),mpc8xx)
-ELF    = test_burst
-SREC   = test_burst.srec
-BIN    = test_burst.bin
+ELF    += test_burst
+SREC   += test_burst.srec
+BIN    += test_burst.bin
 endif
 
 ifeq ($(ARCH),i386)