u32 cpu_rev; /* rev of given cpu; ES1, ES2,...*/
} h4_sys_data;
-#define SDR_DISCRETE 4
+#define XDR_POP 5 /* package on package part */
+#define SDR_DISCRETE 4 /* 128M memory SDR module*/
#define DDR_STACKED 3 /* stacked part on 2422 */
#define DDR_COMBO 2 /* combo part on cpu daughter card (menalaeus) */
#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */
#define DDR_165 165 /* future parts */
#define CPU_2420 0x2420
-#define CPU_2422 0x2422
+#define CPU_2422 0x2422 /* 2420 + 64M stacked */
+#define CPU_2423 0x2423 /* 2420 + 96M stacked */
#define CPU_2422_ES1 1
#define CPU_2422_ES2 2
#define CPU_2420_ES1 1
#define CPU_2420_ES2 2
+#define CPU_2420_2422_ES1 1
#define CPU_2420_CHIPID 0x0B5D9000
#define CPU_24XX_ID_MASK 0x0FFFF000
#define CPU_242X_REV_MASK 0xF0000000
+#define CPU_242X_PID_MASK 0x000F0000
#define BOARD_H4_MENELAUS 1
#define BOARD_H4_SDP 2