MX31: Add NAND SPL boot support to i.MX31 PDK board.

[u-boot] / include / asm-arm / arch-mx31 / mx31-regs.h

diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h
index 76f4d53a32e4a572c6b21671e68a3f6588b6ffb4..51b02a2a2604e335e9c4af3ca7cad2eab4e2aac3 100644 (file)
--- a/include/asm-arm/arch-mx31/mx31-regs.h
+++ b/include/asm-arm/arch-mx31/mx31-regs.h
@@ -61,6 +61,29 @@
 #define PLL_MFI(x)             (((x) & 0xf) << 10)
 #define PLL_MFN(x)             (((x) & 0x3ff) << 0)
 
+#define WEIM_ESDCTL0   0xB8001000
+#define WEIM_ESDCFG0   0xB8001004
+#define WEIM_ESDCTL1   0xB8001008
+#define WEIM_ESDCFG1   0xB800100C
+#define WEIM_ESDMISC   0xB8001010
+
+#define ESDCTL_SDE                     (1 << 31)
+#define ESDCTL_CMD_RW                  (0 << 28)
+#define ESDCTL_CMD_PRECHARGE           (1 << 28)
+#define ESDCTL_CMD_AUTOREFRESH         (2 << 28)
+#define ESDCTL_CMD_LOADMODEREG         (3 << 28)
+#define ESDCTL_CMD_MANUALREFRESH       (4 << 28)
+#define ESDCTL_ROW_13                  (2 << 24)
+#define ESDCTL_ROW(x)                  ((x) << 24)
+#define ESDCTL_COL_9                   (1 << 20)
+#define ESDCTL_COL(x)                  ((x) << 20)
+#define ESDCTL_DSIZ(x)                 ((x) << 16)
+#define ESDCTL_SREFR(x)                        ((x) << 13)
+#define ESDCTL_PWDT(x)                 ((x) << 10)
+#define ESDCTL_FP(x)                   ((x) << 8)
+#define ESDCTL_BL(x)                   ((x) << 7)
+#define ESDCTL_PRCT(x)                 ((x) << 0)
+
 #define WEIM_BASE      0xb8002000
 #define CSCR_U(x)      (WEIM_BASE + (x) * 0x10)
 #define CSCR_L(x)      (WEIM_BASE + 4 + (x) * 0x10)
@@ -181,6 +204,37 @@
 #define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
 #define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
 
+/* PAD control registers for SDR/DDR */
+#define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C)
+#define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0      (IOMUXC_BASE + 0x270)
+#define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS          (IOMUXC_BASE + 0x274)
+#define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA          (IOMUXC_BASE + 0x278)
+#define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4          (IOMUXC_BASE + 0x27C)
+#define IOMUXC_SW_PAD_CTL_OE_CS0_CS1           (IOMUXC_BASE + 0x280)
+#define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1         (IOMUXC_BASE + 0x284)
+#define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2       (IOMUXC_BASE + 0x288)
+#define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31       (IOMUXC_BASE + 0x28C)
+#define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28       (IOMUXC_BASE + 0x290)
+#define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25       (IOMUXC_BASE + 0x294)
+#define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22       (IOMUXC_BASE + 0x298)
+#define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19       (IOMUXC_BASE + 0x29C)
+#define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16       (IOMUXC_BASE + 0x2A0)
+#define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13       (IOMUXC_BASE + 0x2A4)
+#define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10         (IOMUXC_BASE + 0x2A8)
+#define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7          (IOMUXC_BASE + 0x2AC)
+#define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4          (IOMUXC_BASE + 0x2B0)
+#define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1                (IOMUXC_BASE + 0x2B4)
+#define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1                (IOMUXC_BASE + 0x2B8)
+#define IOMUXC_SW_PAD_CTL_A21_A22_A23          (IOMUXC_BASE + 0x2BC)
+#define IOMUXC_SW_PAD_CTL_A18_A19_A20          (IOMUXC_BASE + 0x2C0)
+#define IOMUXC_SW_PAD_CTL_A15_A16_A17          (IOMUXC_BASE + 0x2C4)
+#define IOMUXC_SW_PAD_CTL_A12_A13_A14          (IOMUXC_BASE + 0x2C8)
+#define IOMUXC_SW_PAD_CTL_A10_MA10_A11         (IOMUXC_BASE + 0x2CC)
+#define IOMUXC_SW_PAD_CTL_A7_A8_A9             (IOMUXC_BASE + 0x2D0)
+#define IOMUXC_SW_PAD_CTL_A4_A5_A6             (IOMUXC_BASE + 0x2D4)
+#define IOMUXC_SW_PAD_CTL_A1_A2_A3             (IOMUXC_BASE + 0x2D8)
+#define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0         (IOMUXC_BASE + 0x2DC)
+
 /*
  * Memory regions and CS
  */