#define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */
#define ICR_TB 0x8 /* transfer byte bit */
#define ICR_MA 0x10 /* master abort */
-#define ICR_SCLE 0x20 /* master clock enable */
+#define ICR_SCLE 0x20 /* master clock enable, mona SCLEA */
#define ICR_IUE 0x40 /* unit enable */
#define ICR_GCD 0x80 /* general call disable */
#define ICR_ITEIE 0x100 /* enable tx interrupts */
-#define ICR_IRFIE 0x200 /* enable rx interrupts */
+#define ICR_IRFIE 0x200 /* enable rx interrupts, mona: DRFIE */
#define ICR_BEIE 0x400 /* enable bus error ints */
#define ICR_SSDIE 0x800 /* slave STOP detected int enable */
#define ICR_ALDIE 0x1000 /* enable arbitration interrupt */
#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
+
/*
* USB Device Controller
*/
+#ifndef CONFIG_CPU_MONAHANS
#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */
#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */
#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
+#endif /* ! CONFIG_CPU_MONAHANS */
+
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+
+/*
+ * USB Client Controller (incomplete)
+ */
+#define UDCCR __REG(0x40600000)
+#define UDCICR0 __REG(0x40600004)
+#define UDCCIR0 __REG(0x40600008)
+#define UDCISR0 __REG(0x4060000c)
+#define UDCSIR1 __REG(0x40600010)
+#define UDCFNR __REG(0x40600014)
+#define UDCOTGICR __REG(0x40600018)
+#define UDCOTGISR __REG(0x4060001c)
+#define UP2OCR __REG(0x40600020)
+#define UP3OCR __REG(0x40600024)
-#if defined(CONFIG_PXA27X)
/*
* USB Host Controller
*/
+#define OHCI_REGS_BASE 0x4C000000 /* required for ohci driver */
#define UHCREV __REG(0x4C000000)
#define UHCHCON __REG(0x4C000004)
#define UHCCOMS __REG(0x4C000008)
#define RTAR __REG(0x40900004) /* RTC Alarm Register */
#define RTSR __REG(0x40900008) /* RTC Status Register */
#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
-#define RDAR1 __REG(0x40900018) /* Wristwatch Day Alarm Reg 1 */
-#define RDAR2 __REG(0x40900020) /* Wristwatch Day Alarm Reg 2 */
-#define RYAR1 __REG(0x4090001C) /* Wristwatch Year Alarm Reg 1 */
-#define RYAR2 __REG(0x40900024) /* Wristwatch Year Alarm Reg 2 */
-#define SWAR1 __REG(0x4090002C) /* Stopwatch Alarm Register 1 */
-#define SWAR2 __REG(0x40900030) /* Stopwatch Alarm Register 2 */
-#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
-#define RDCR __REG(0x40900010) /* RTC Day Count Register. */
-#define RYCR __REG(0x40900014) /* RTC Year Count Register. */
-#define SWCR __REG(0x40900028) /* Stopwatch Count Register */
-#define RTCPICR __REG(0x40900034) /* Periodic Interrupt Counter Register */
-
-#define RTSR_PICE (1 << 15) /* Peridoc interrupt count enable */
-#define RTSR_PIALE (1 << 14) /* Peridoc interrupt Alarm enable */
-#define RTSR_PIAL (1 << 13) /* Peridoc interrupt Alarm status */
+#define RDAR1 __REG(0x40900018) /* Wristwatch Day Alarm Reg 1 */
+#define RDAR2 __REG(0x40900020) /* Wristwatch Day Alarm Reg 2 */
+#define RYAR1 __REG(0x4090001C) /* Wristwatch Year Alarm Reg 1 */
+#define RYAR2 __REG(0x40900024) /* Wristwatch Year Alarm Reg 2 */
+#define SWAR1 __REG(0x4090002C) /* Stopwatch Alarm Register 1 */
+#define SWAR2 __REG(0x40900030) /* Stopwatch Alarm Register 2 */
+#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
+#define RDCR __REG(0x40900010) /* RTC Day Count Register. */
+#define RYCR __REG(0x40900014) /* RTC Year Count Register. */
+#define SWCR __REG(0x40900028) /* Stopwatch Count Register */
+#define RTCPICR __REG(0x40900034) /* Periodic Interrupt Counter Register */
+
+#define RTSR_PICE (1 << 15) /* Peridoc interrupt count enable */
+#define RTSR_PIALE (1 << 14) /* Peridoc interrupt Alarm enable */
+#define RTSR_PIAL (1 << 13) /* Peridoc interrupt Alarm status */
#define RTSR_HZE (1 << 3) /* HZ interrupt enable */
#define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
#define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
#define OMCR9 __REG(0x40A000D4) /* OS Match Control Register 9 */
#define OMCR10 __REG(0x40A000D8) /* OS Match Control Register 10 */
#define OMCR11 __REG(0x40A000DC) /* OS Match Control Register 11 */
+
+#define OSCR_CLK_FREQ 3.250 /* MHz */
#endif /* CONFIG_CPU_MONAHANS */
#define OSSR_M4 (1 << 4) /* Match status channel 4 */
#ifdef CONFIG_CPU_MONAHANS
#define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */
-/* Missing: 32 Interrupt priority registers */
-/* mk@tbd: These are the same as beneath for PXA27x: maybe can be
- * merged if GPIO Stuff is same too. */
+/* Missing: 32 Interrupt priority registers
+ * These are the same as beneath for PXA27x: maybe can be merged if
+ * GPIO Stuff is same too.
+ */
#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
#define GCDR3 __REG(0x40E0042C) /* Bit-wise Clear of GPDR[127:96] */
#define GSRER0 __REG(0x40E00440) /* Set Rising Edge Det. Enable [31:0] */
-#define GSRER1 __REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */
+#define GSRER1 __REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */
#define GSRER2 __REG(0x40E00448) /* Set Rising Edge Det. Enable [95:64] */
-#define GSRER3 __REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */
+#define GSRER3 __REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */
#define GCRER0 __REG(0x40E00460) /* Clear Rising Edge Det. Enable [31:0] */
-#define GCRER1 __REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */
+#define GCRER1 __REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */
#define GCRER2 __REG(0x40E00468) /* Clear Rising Edge Det. Enable [95:64] */
-#define GCRER3 __REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */
+#define GCRER3 __REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */
#define GSFER0 __REG(0x40E00480) /* Set Falling Edge Det. Enable [31:0] */
-#define GSFER1 __REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */
+#define GSFER1 __REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */
#define GSFER2 __REG(0x40E00488) /* Set Falling Edge Det. Enable [95:64] */
-#define GSFER3 __REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */
+#define GSFER3 __REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */
#define GCFER0 __REG(0x40E004A0) /* Clr Falling Edge Det. Enable [31:0] */
-#define GCFER1 __REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */
+#define GCFER1 __REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */
#define GCFER2 __REG(0x40E004A8) /* Clr Falling Edge Det. Enable [95:64] */
-#define GCFER3 __REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */
+#define GCFER3 __REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */
#define GSDR(x) __REG2(0x40E00400, ((x) & 0x60) >> 3)
#define GCDR(x) __REG2(0x40300420, ((x) & 0x60) >> 3)
-/* Multi-funktion Pin Registers, uncomplete, only GPIO relevant pins for now */
-#define GPIO0 __REG(0x40e10124)
+/* Multi-funktion Pin Registers, uncomplete, only:
+ * - GPIO
+ * - Data Flash DF_* pins defined.
+ */
+#define GPIO0 __REG(0x40e10124)
#define GPIO1 __REG(0x40e10128)
#define GPIO2 __REG(0x40e1012c)
#define GPIO3 __REG(0x40e10130)
#define GPIO4 __REG(0x40e10134)
+#define nXCVREN __REG(0x40e10138)
+
+#define DF_CLE_NOE __REG(0x40e10204)
+#define DF_ALE_WE1 __REG(0x40e10208)
+
+#define DF_SCLK_E __REG(0x40e10210)
+#define nBE0 __REG(0x40e10214)
+#define nBE1 __REG(0x40e10218)
+#define DF_ALE_WE2 __REG(0x40e1021c)
+#define DF_INT_RnB __REG(0x40e10220)
+#define DF_nCS0 __REG(0x40e10224)
+#define DF_nCS1 __REG(0x40e10228)
+#define DF_nWE __REG(0x40e1022c)
+#define DF_nRE __REG(0x40e10230)
+#define nLUA __REG(0x40e10234)
+#define nLLA __REG(0x40e10238)
+#define DF_ADDR0 __REG(0x40e1023c)
+#define DF_ADDR1 __REG(0x40e10240)
+#define DF_ADDR2 __REG(0x40e10244)
+#define DF_ADDR3 __REG(0x40e10248)
+#define DF_IO0 __REG(0x40e1024c)
+#define DF_IO8 __REG(0x40e10250)
+#define DF_IO1 __REG(0x40e10254)
+#define DF_IO9 __REG(0x40e10258)
+#define DF_IO2 __REG(0x40e1025c)
+#define DF_IO10 __REG(0x40e10260)
+#define DF_IO3 __REG(0x40e10264)
+#define DF_IO11 __REG(0x40e10268)
+#define DF_IO4 __REG(0x40e1026c)
+#define DF_IO12 __REG(0x40e10270)
+#define DF_IO5 __REG(0x40e10274)
+#define DF_IO13 __REG(0x40e10278)
+#define DF_IO6 __REG(0x40e1027c)
+#define DF_IO14 __REG(0x40e10280)
+#define DF_IO7 __REG(0x40e10284)
+#define DF_IO15 __REG(0x40e10288)
#define GPIO5 __REG(0x40e1028c)
#define GPIO6 __REG(0x40e10290)
#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
-#define GPLR(x) ((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)
-#define GPDR(x) ((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)
-#define GPSR(x) ((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)
-#define GPCR(x) ((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)
-#define GRER(x) ((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)
-#define GFER(x) ((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)
-#define GEDR(x) ((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)
-#define GAFR(x) ((((x) & 0x7f) < 96) ? _GAFR(x) : \
- ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))
+#define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
+#define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
+#define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
+#define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
+#define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
+#define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
+#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
+#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
+ ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
#else
#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
#define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT)
#define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT)
-#define GPIO117_SCL (117 | GPIO_ALT_FN_1_OUT)
-#define GPIO118_SDA (118 | GPIO_ALT_FN_1_OUT)
+#define GPIO117_SCL (117 | GPIO_ALT_FN_1_OUT)
+#define GPIO118_SDA (118 | GPIO_ALT_FN_1_OUT)
/*
* Power Manager
#define ACCR_13MEND2 (1 << 21)
#define ACCR_PCCE (1 << 11)
-#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */
-#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */
-#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */
-#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */
+#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */
+#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */
+#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */
+#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */
#define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */
#define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */
#define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */
#define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */
#define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */
#define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */
-#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */
-#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */
-#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */
-#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */
-#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */
-#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */
-#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */
-#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */
-#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */
-#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */
-#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */
-#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */
+#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */
+#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */
+#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */
+#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */
+#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */
+#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */
+#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */
+#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */
+#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */
+#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */
+#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */
+#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */
#define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */
-#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */
-#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */
+#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */
+#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */
#define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */
#define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */
#define CKENB_8_1WIRE ((1 << 8) + 32) /* One Wire Interface Unit Clock Enable */
-#define CKENB_7_GPIO ((1 << 7) + 32) /* GPIO Clock Enable */
-#define CKENB_6_IRQ ((1 << 6) + 32) /* Interrupt Controller Clock Enable */
+#define CKENB_7_GPIO ((1 << 7) + 32) /* GPIO Clock Enable */
+#define CKENB_6_IRQ ((1 << 6) + 32) /* Interrupt Controller Clock Enable */
#define CKENB_4_I2C ((1 << 4) + 32) /* I2C Unit Clock Enable */
#define CKENB_1_PWM1 ((1 << 1) + 32) /* PWM2 & PWM3 Clock Enable */
#define CKENB_0_PWM0 ((1 << 0) + 32) /* PWM0 & PWM1 Clock Enable */
#define PAD_SCLK __REG_2(0x4810012C)
#define TAI __REG_2(0x48100F00) /* TAI Tavor Address Isolation Register */
+/* Some frequently used bits */
+#define MDCNFG_DMAP 0x80000000 /* SDRAM 1GB Memory Map Enable */
+#define MDCNFG_DMCEN 0x40000000 /* Enable Dynamic Memory Controller */
+#define MDCNFG_HWFREQ 0x20000000 /* Hardware Frequency Change Calibration */
+#define MDCNFG_DTYPE 0x400 /* SDRAM Type: 1=DDR SDRAM */
+
+#define MDCNFG_DTC_0 0x0 /* Timing Category of SDRAM */
+#define MDCNFG_DTC_1 0x100
+#define MDCNFG_DTC_2 0x200
+#define MDCNFG_DTC_3 0x300
+
+#define MDCNFG_DRAC_12 0x0 /* Number of Row Access Bits */
+#define MDCNFG_DRAC_13 0x20
+#define MDCNFG_DRAC_14 0x40
+
+#define MDCNFG_DCAC_9 0x0 /* Number of Column Acess Bits */
+#define MDCNFG_DCAC_10 0x08
+#define MDCNFG_DCAC_11 0x10
+
+#define MDCNFG_DBW_16 0x4 /* SDRAM Data Bus width 16bit */
+#define MDCNFG_DCSE1 0x2 /* SDRAM CS 1 Enable */
+#define MDCNFG_DCSE0 0x1 /* SDRAM CS 0 Enable */
+
/* Data Flash Controller Registers */
-#define NDCR __REG_2(0x43100000) /* Data Flash Control register */
-#define NDTR0CS0 __REG_2(0x43100004) /* Data Controller Timing Parameter 0 Register for ND_nCS0 */
-#define NDTR0CS1 __REG_2(0x43100008) /* Data Controller Timing Parameter 0 Register for ND_nCS1 */
-#define NDTR1CS0 __REG_2(0x4310000C) /* Data Controller Timing Parameter 1 Register for ND_nCS0 */
-#define NDTR1CS1 __REG_2(0x43100010) /* Data Controller Timing Parameter 1 Register for ND_nCS1 */
-#define NDSR __REG_2(0x43100014) /* Data Controller Status Register */
-#define NDPCR __REG_2(0x43100018) /* Data Controller Page Count Register */
-#define NDBDR0 __REG_2(0x4310001C) /* Data Controller Bad Block Register 0 */
-#define NDBDR1 __REG_2(0x43100020) /* Data Controller Bad Block Register 1 */
-#define NDDB __REG_2(0x43100040) /* Data Controller Data Buffer */
-#define NDCB0 __REG_2(0x43100048) /* Data Controller Command Buffer0 */
-#define NDCB1 __REG_2(0x4310004C) /* Data Controller Command Buffer1 */
-#define NDCB2 __REG_2(0x43100050) /* Data Controller Command Buffer2 */
+#define NDCR __REG(0x43100000) /* Data Flash Control register */
+#define NDTR0CS0 __REG(0x43100004) /* Data Controller Timing Parameter 0 Register for ND_nCS0 */
+/* #define NDTR0CS1 __REG(0x43100008) /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */
+#define NDTR1CS0 __REG(0x4310000C) /* Data Controller Timing Parameter 1 Register for ND_nCS0 */
+/* #define NDTR1CS1 __REG(0x43100010) /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */
+#define NDSR __REG(0x43100014) /* Data Controller Status Register */
+#define NDPCR __REG(0x43100018) /* Data Controller Page Count Register */
+#define NDBDR0 __REG(0x4310001C) /* Data Controller Bad Block Register 0 */
+#define NDBDR1 __REG(0x43100020) /* Data Controller Bad Block Register 1 */
+#define NDDB __REG(0x43100040) /* Data Controller Data Buffer */
+#define NDCB0 __REG(0x43100048) /* Data Controller Command Buffer0 */
+#define NDCB1 __REG(0x4310004C) /* Data Controller Command Buffer1 */
+#define NDCB2 __REG(0x43100050) /* Data Controller Command Buffer2 */
#define NDCR_SPARE_EN (0x1<<31)
#define NDCR_ECC_EN (0x1<<30)
#define NDCR_DWIDTH_M (0x1<<26)
#define NDCR_PAGE_SZ (0x3<<24)
#define NDCR_NCSX (0x1<<23)
-#define NDCR_ND_MODE (0x3<<21)
-#define NDCR_NAND_MODE 0x0
+#define NDCR_ND_STOP (0x1<<22)
+/* reserved:
+ * #define NDCR_ND_MODE (0x3<<21)
+ * #define NDCR_NAND_MODE 0x0 */
#define NDCR_CLR_PG_CNT (0x1<<20)
#define NDCR_CLR_ECC (0x1<<19)
#define NDCR_RD_ID_CNT (0x7<<16)
#define NDCR_RA_START (0x1<<15)
#define NDCR_PG_PER_BLK (0x1<<14)
#define NDCR_ND_ARB_EN (0x1<<12)
+#define NDCR_RDYM (0x1<<11)
+#define NDCR_CS0_PAGEDM (0x1<<10)
+#define NDCR_CS1_PAGEDM (0x1<<9)
+#define NDCR_CS0_CMDDM (0x1<<8)
+#define NDCR_CS1_CMDDM (0x1<<7)
+#define NDCR_CS0_BBDM (0x1<<6)
+#define NDCR_CS1_BBDM (0x1<<5)
+#define NDCR_DBERRM (0x1<<4)
+#define NDCR_SBERRM (0x1<<3)
+#define NDCR_WRDREQM (0x1<<2)
+#define NDCR_RDDREQM (0x1<<1)
+#define NDCR_WRCMDREQM (0x1)
#define NDSR_RDY (0x1<<11)
#define NDSR_CS0_PAGED (0x1<<10)
#define NDSR_CS1_CMDD (0x1<<7)
#define NDSR_CS0_BBD (0x1<<6)
#define NDSR_CS1_BBD (0x1<<5)
-#define NDSR_BDERR (0x1<<4)
+#define NDSR_DBERR (0x1<<4)
#define NDSR_SBERR (0x1<<3)
#define NDSR_WRDREQ (0x1<<2)
#define NDSR_RDDREQ (0x1<<1)
#define MCIO(s) MCIO0
#define MECR_CIT (1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */
+/* Maximum values for NAND Interface Timing Registers in DFC clock
+ * periods */
+#define DFC_MAX_tCH 7
+#define DFC_MAX_tCS 7
+#define DFC_MAX_tWH 7
+#define DFC_MAX_tWP 7
+#define DFC_MAX_tRH 7
+#define DFC_MAX_tRP 15
+#define DFC_MAX_tR 65535
+#define DFC_MAX_tWHR 15
+#define DFC_MAX_tAR 15
+
+#define DFC_CLOCK 104 /* DFC Clock is 104 MHz */
+#define DFC_CLK_PER_US DFC_CLOCK/1000 /* clock period in ns */
+
#else /* CONFIG_CPU_MONAHANS */
#define MEMC_BASE __REG(0x48000000) /* Base of Memory Controller */
#define KPAS_SO (0x1 << 31)
#define KPASMKPx_SO (0x1 << 31)
-#define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
-#define PSLR __REG(0x40F00034)
-#define PSTR __REG(0x40F00038) /* Power Manager Standby Configuration Reg */
-#define PSNR __REG(0x40F0003C) /* Power Manager Sense Configuration Reg */
-#define PVCR __REG(0x40F00040) /* Power Manager Voltage Change Control Reg */
-#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-Up Enable Reg */
-#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Status Reg */
-#define OSMR4 __REG(0x40A00080) /* */
-#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
-#define OMCR4 __REG(0x40A000C0) /* */
+#define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
+#define PSLR __REG(0x40F00034)
+#define PSTR __REG(0x40F00038) /* Power Manager Standby Configuration Reg */
+#define PSNR __REG(0x40F0003C) /* Power Manager Sense Configuration Reg */
+#define PVCR __REG(0x40F00040) /* Power Manager Voltage Change Control Reg */
+#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-Up Enable Reg */
+#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Status Reg */
+#define OSMR4 __REG(0x40A00080) /* */
+#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
+#define OMCR4 __REG(0x40A000C0) /* */
#endif /* CONFIG_PXA27X */
projects / u-boot / blobdiff