Merge branch 'master' of git://git.denx.de/u-boot-at91

[u-boot] / include / asm-blackfin / mach-common / ADSP-EDN-extended_cdef.h

diff --git a/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h b/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h
index 2f5a2658fbfb9e6f887896e6de02c931bc9f580b..2e61b5faae819d61ef520af52788cf4cee74d836 100644 (file)
--- a/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h
+++ b/include/asm-blackfin/mach-common/ADSP-EDN-extended_cdef.h
@@ -897,18 +897,15 @@
 #define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count register (16-bit) */
 #define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
 #define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define pSWRST                         ((uint32_t volatile *)SWRST) /* Software Reset Register (16-bit) */
-#define bfin_read_SWRST()              bfin_read32(SWRST)
-#define bfin_write_SWRST(val)          bfin_write32(SWRST, val)
-#define pSYSCR                         ((uint32_t volatile *)SYSCR) /* System Configuration register */
-#define bfin_read_SYSCR()              bfin_read32(SYSCR)
-#define bfin_write_SYSCR(val)          bfin_write32(SYSCR, val)
+#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register (16-bit) */
+#define bfin_read_SWRST()              bfin_read16(SWRST)
+#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
+#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */
+#define bfin_read_SYSCR()              bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
 #define pEVT_OVERRIDE                  ((uint32_t volatile *)EVT_OVERRIDE)
 #define bfin_read_EVT_OVERRIDE()       bfin_read32(EVT_OVERRIDE)
 #define bfin_write_EVT_OVERRIDE(val)   bfin_write32(EVT_OVERRIDE, val)
-#define pDSPID                         ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID()              bfin_read32(DSPID)
-#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
 #define pCHIPID                        ((uint32_t volatile *)CHIPID)
 #define bfin_read_CHIPID()             bfin_read32(CHIPID)
 #define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
@@ -1042,7 +1039,6 @@
 #define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
 #define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
 #define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */
-#define bfin_read_SPORT0_TX()          bfin_read32(SPORT0_TX)
 #define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
 #define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */
 #define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
@@ -1084,7 +1080,6 @@
 #define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
 #define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
 #define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 TX Data Register */
-#define bfin_read_SPORT1_TX()          bfin_read32(SPORT1_TX)
 #define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
 #define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 RX Data Register */
 #define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)