8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx

[u-boot] / include / asm-ppc / cpm_8260.h

diff --git a/include/asm-ppc/cpm_8260.h b/include/asm-ppc/cpm_8260.h
index bf2e2a2cb62c6c3bc1b743ce42225f166c6ae8c0..8302404abb5860f361c4de30b91f859203423f7a 100644 (file)
--- a/include/asm-ppc/cpm_8260.h
+++ b/include/asm-ppc/cpm_8260.h
@@ -83,9 +83,14 @@
  * downloading RAM microcode.
  */
 #define CPM_DATAONLY_BASE      ((uint)128)
-#define CPM_DATAONLY_SIZE      ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
 #define CPM_DP_NOSPACE         ((uint)0x7fffffff)
+#ifndef CONFIG_MPC8272_FAMILY
+#define CPM_DATAONLY_SIZE      ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
 #define CPM_FCC_SPECIAL_BASE   ((uint)0x0000b000)
+#else  /* 8247/48/71/72 */
+#define CPM_DATAONLY_SIZE      ((uint)(4 * 1024) - CPM_DATAONLY_BASE)
+#define CPM_FCC_SPECIAL_BASE   ((uint)0x00009000)
+#endif /* !CONFIG_MPC8272_FAMILY */
 
 /* The number of pages of host memory we allocate for CPM.  This is
  * done early in kernel initialization to get physically contiguous
@@ -136,11 +141,18 @@ typedef struct cpm_buf_desc {
 
 /* Parameter RAM offsets from the base.
 */
-#ifndef CFG_CPM_POST_WORD_ADDR
+#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR
 #define CPM_POST_WORD_ADDR      0x80FC /* steal a long at the end of SCC1 */
 #else
-#define CPM_POST_WORD_ADDR     CFG_CPM_POST_WORD_ADDR
+#define CPM_POST_WORD_ADDR     CONFIG_SYS_CPM_POST_WORD_ADDR
 #endif
+
+#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
+#define CPM_BOOTCOUNT_ADDR     (CPM_POST_WORD_ADDR - 2*sizeof(ulong))
+#else
+#define CPM_BOOTCOUNT_ADDR     CONFIG_SYS_CPM_BOOTCOUNT_ADDR
+#endif
+
 #define PROFF_SCC1             ((uint)0x8000)
 #define PROFF_SCC2             ((uint)0x8100)
 #define PROFF_SCC3             ((uint)0x8200)
@@ -170,7 +182,7 @@ typedef struct cpm_buf_desc {
  */
 #define PROFF_SMC1     (0)
 #define PROFF_SMC2     (64)
-
+#define PROFF_SPI      ((16*1024) - 128)
 
 /* Define enough so I can at least use the serial port as a UART.
  */
@@ -534,6 +546,34 @@ typedef struct scc_trans {
 
 #define BD_SCC_TX_LAST         ((ushort)0x0800)
 
+/*  SCC as HDLC controller - taken from commproc.h
+ */
+typedef struct scc_hdlc {
+       sccp_t  sh_genscc;
+       /*
+       * HDLC specific parameter RAM
+       */
+       uchar   res[4];         /* reserved */
+       ulong   sh_cmask;       /* CRC constant */
+       ulong   sh_cpres;       /* CRC preset */
+       ushort  sh_disfc;       /* discarded frame counter */
+       ushort  sh_crcec;       /* CRC error counter */
+       ushort  sh_abtsc;       /* abort sequence counter */
+       ushort  sh_nmarc;       /* nonmatching address rx cnt */
+       ushort  sh_retrc;       /* frame retransmission cnt */
+       ushort  sh_mflr;        /* maximum frame length reg */
+       ushort  sh_maxcnt;      /* maximum length counter */
+       ushort  sh_rfthr;       /* received frames threshold */
+       ushort  sh_rfcnt;       /* received frames count */
+       ushort  sh_hmask;       /* user defined frm addr mask */
+       ushort  sh_haddr1;      /* user defined frm address 1 */
+       ushort  sh_haddr2;      /* user defined frm address 2 */
+       ushort  sh_haddr3;      /* user defined frm address 3 */
+       ushort  sh_haddr4;      /* user defined frm address 4 */
+       ushort  tmp;            /* temp */
+       ushort  tmp_mb;         /* temp */
+} scc_hdlc_t;
+
 /* How about some FCCs.....
 */
 #define FCC_GFMR_DIAG_NORM     ((uint)0x00000000)
@@ -676,6 +716,7 @@ typedef struct fcc_enet {
 #define FCC_PSMR_PRO   ((uint)0x00400000)      /* Promiscuous Enable */
 #define FCC_PSMR_FCE   ((uint)0x00200000)      /* Flow Control Enable */
 #define FCC_PSMR_RSH   ((uint)0x00100000)      /* Receive Short Frames */
+#define FCC_PSMR_RMII  ((uint)0x00020000)      /* Use RMII interface */
 #define FCC_PSMR_CAM   ((uint)0x00000400)      /* CAM enable */
 #define FCC_PSMR_BRO   ((uint)0x00000200)      /* Broadcast pkt discard */
 #define FCC_PSMR_ENCRC ((uint)0x00000080)      /* Use 32-bit CRC */
@@ -737,6 +778,17 @@ typedef struct spi {
 #define SPMODE_LEN(x)  ((((x)-1)&0xF)<<4)
 #define SPMODE_PM(x)   ((x) &0xF)
 
+/* SPI Event/Mask register.
+*/
+#define SPI_EMASK              0x37    /* Event Mask                           */
+#define SPI_MME                        0x20    /* Multi-Master Error                   */
+#define SPI_TXE                        0x10    /* Transmit Error                       */
+#define SPI_BSY                        0x04    /* Busy                                 */
+#define SPI_TXB                        0x02    /* Tx Buffer Empty                      */
+#define SPI_RXB                        0x01    /* RX Buffer full/closed                */
+
+#define SPI_STR                        0x80    /* SPCOM: Start transmit                */
+
 #define SPI_EB         ((u_char)0x10)          /* big endian byte order */
 
 #define BD_IIC_START           ((ushort)0x0400)