ppc/8xxx: Refactor code to determine if PCI is enabled & agent/host

[u-boot] / include / asm-ppc / fsl_pci.h

diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h
index 624ca5685a9115f29cf5fa561dc0a56d7f7c0036..b9972dabe37758968ecbd3802b3bd8e4d8121bc8 100644 (file)
--- a/include/asm-ppc/fsl_pci.h
+++ b/include/asm-ppc/fsl_pci.h
@@ -20,8 +20,12 @@
 #ifndef __FSL_PCI_H_
 #define __FSL_PCI_H_
 
-int fsl_pci_setup_inbound_windows(struct pci_region *r);
-void fsl_pci_init(struct pci_controller *hose);
+#include <asm/fsl_law.h>
+
+int is_fsl_pci_agent(enum law_trgt_if trgt, u32 host_agent);
+int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel);
+
+void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data);
 void fsl_pci_config_unlock(struct pci_controller *hose);
 void ft_fsl_pci_setup(void *blob, const char *pci_alias,
                        struct pci_controller *hose);
@@ -155,4 +159,30 @@ typedef struct ccsr_pci {
        char    res24[252];
 } ccsr_fsl_pci_t;
 
+struct fsl_pci_info {
+       unsigned long   regs;
+       pci_addr_t      mem_bus;
+       phys_size_t     mem_phys;
+       pci_size_t      mem_size;
+       pci_addr_t      io_bus;
+       phys_size_t     io_phys;
+       pci_size_t      io_size;
+       int             pci_num;
+};
+
+int fsl_pci_init_port(struct fsl_pci_info *pci_info,
+                               struct pci_controller *hose, int busno);
+
+#define SET_STD_PCIE_INFO(x, num) \
+{                      \
+       x.regs = CONFIG_SYS_PCIE##num##_ADDR;   \
+       x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
+       x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
+       x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
+       x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
+       x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
+       x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
+       x.pci_num = num; \
+}
+
 #endif