u8 res0[4];
u32 bcr; /* Bread Crumb Register */
u32 pscccr[12]; /* PSC0-11 Clock Control Registers */
- u32 spccr; /* SPDIF Clock Control Registers */
- u32 cccr; /* CFM Clock Control Registers */
- u32 dccr; /* DIU Clock Control Registers */
- u8 res1[0xa8];
+ u32 spccr; /* SPDIF Clock Control Register */
+ u32 cccr; /* CFM Clock Control Register */
+ u32 dccr; /* DIU Clock Control Register */
+ u32 msccr[4]; /* MSCAN1-4 Clock Control Registers */
+ u8 res1[0x98];
} clk512x_t;
/* SPMR - System PLL Mode Register */
#define SCFR1_PCI_DIV_MASK 0x00700000
#define SCFR1_PCI_DIV_SHIFT 20
+#define SCFR1_LPC_DIV_MASK 0x00003800
+#define SCFR1_LPC_DIV_SHIFT 11
+
/* SCFR2 System Clock Frequency Register 2 */
#define SCFR2_SYS_DIV 0xFC000000
#define SCFR2_SYS_DIV_SHIFT 26