/*
* MPC85xx Internal Memory Map
*
+ * Copyright 2007 Freescale Semiconductor.
+ *
* Copyright(c) 2002,2003 Motorola Inc.
* Xianghua Xiao (x.xiao@motorola.com)
*
#ifndef __IMMAP_85xx__
#define __IMMAP_85xx__
+#include <asm/types.h>
+#include <asm/fsl_i2c.h>
-/* Local-Access Registers and ECM Registers(0x0000-0x2000) */
-
+/*
+ * Local-Access Registers and ECM Registers(0x0000-0x2000)
+ */
typedef struct ccsr_local_ecm {
uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
char res1[4];
uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
char res19[4];
uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
- char res20[780];
+ char res20[780]; /* XXX: LAW 8, LAW9 for 8572 */
uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */
char res21[12];
uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */
char res24[492];
} ccsr_local_ecm_t;
-
-/* DDR memory controller registers(0x2000-0x3000) */
-
+/*
+ * DDR memory controller registers(0x2000-0x3000)
+ */
typedef struct ccsr_ddr {
uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
char res1[4];
uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
- char res5[120];
+ char res4a[48];
+ uint cs0_config_2; /* 0x20c0 - DDR Chip Select Configuration 2 */
+ uint cs1_config_2; /* 0x20c4 - DDR Chip Select Configuration 2 */
+ uint cs2_config_2; /* 0x20c8 - DDR Chip Select Configuration 2 */
+ uint cs3_config_2; /* 0x20cc - DDR Chip Select Configuration 2 */
+ char res5[48];
+ uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
+ uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration */
- char res6[4];
+ uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration */
- char res7[8];
+ uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2*/
+ uint sdram_md_cntl; /* 0x2120 - DDR SDRAM Mode Control */
uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
-#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
- char res7_5[8];
+ uint sdram_data_init; /* 0x2128 - DDR SDRAM Data initialization */
+ char res6[4];
uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
- char res8[3276];
-#else
- char res8[3288];
-#endif
+ char res7[20];
+ uint init_addr; /* 0x2148 - DDR training initialization address */
+ uint init_ext_addr; /* 0x214C - DDR training initialization extended address */
+ char res8_1[16];
+ uint timing_cfg_4; /* 0x2160 - DDR SDRAM Timing Configuration Register 4 */
+ uint timing_cfg_5; /* 0x2164 - DDR SDRAM Timing Configuration Register 5 */
+ char reg8_1a[8];
+ uint ddr_zq_cntl; /* 0x2170 - DDR ZQ calibration control*/
+ uint ddr_wrlvl_cntl; /* 0x2174 - DDR write leveling control*/
+ uint ddr_pd_cntl; /* 0x2178 - DDR pre-drive conditioning control*/
+ uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */
+ uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */
+ uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */
+ char res8_1b[2672];
+ uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
+ uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
+ char res8_2[512];
uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
char res12[240];
} ccsr_ddr_t;
-
-/* I2C Registers(0x3000-0x4000) */
-
+/*
+ * I2C Registers(0x3000-0x4000)
+ */
typedef struct ccsr_i2c {
- u_char i2cadr; /* 0x3000 - I2C Address Register */
-#define MPC85xx_I2CADR_MASK 0xFE
- char res1[3];
- u_char i2cfdr; /* 0x3004 - I2C Frequency Divider Register */
-#define MPC85xx_I2CFDR_MASK 0x3F
- char res2[3];
- u_char i2ccr; /* 0x3008 - I2C Control Register */
-#define MPC85xx_I2CCR_MEN 0x80
-#define MPC85xx_I2CCR_MIEN 0x40
-#define MPC85xx_I2CCR_MSTA 0x20
-#define MPC85xx_I2CCR_MTX 0x10
-#define MPC85xx_I2CCR_TXAK 0x08
-#define MPC85xx_I2CCR_RSTA 0x04
-#define MPC85xx_I2CCR_BCST 0x01
- char res3[3];
- u_char i2csr; /* 0x300c - I2C Status Register */
-#define MPC85xx_I2CSR_MCF 0x80
-#define MPC85xx_I2CSR_MAAS 0x40
-#define MPC85xx_I2CSR_MBB 0x20
-#define MPC85xx_I2CSR_MAL 0x10
-#define MPC85xx_I2CSR_BCSTM 0x08
-#define MPC85xx_I2CSR_SRW 0x04
-#define MPC85xx_I2CSR_MIF 0x02
-#define MPC85xx_I2CSR_RXAK 0x01
- char res4[3];
- u_char i2cdr; /* 0x3010 - I2C Data Register */
-#define MPC85xx_I2CDR_DATA 0xFF
- char res5[3];
- u_char i2cdfsrr; /* 0x3014 - I2C Digital Filtering Sampling Rate Register */
-#define MPC85xx_I2CDFSRR 0x3F
- char res6[4075];
+ struct fsl_i2c i2c[1];
+ u8 res[4096 - 1 * sizeof(struct fsl_i2c)];
} ccsr_i2c_t;
#if defined(CONFIG_MPC8540) \
|| defined(CONFIG_MPC8541) \
+ || defined(CONFIG_MPC8548) \
|| defined(CONFIG_MPC8555)
/* DUART Registers(0x4000-0x5000) */
typedef struct ccsr_duart {
char res7[12];
uint lbcr; /* 0x50d0 - LBC Configuration Register */
uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */
- char res8[12072];
+ char res8[3880];
} ccsr_lbc_t;
-
-/* PCI Registers(0x8000-0x9000) */
-/* Omitting Reserved(0x9000-0x2_0000) */
-
+/*
+ * PCI Registers(0x8000-0x9000)
+ */
typedef struct ccsr_pcix {
uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */
uint cfg_data; /* 0x8004 - PCIX Configuration Data Register */
uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */
uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */
uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */
- char res11[94688];
+ uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */
+ char res11[476];
} ccsr_pcix_t;
+#define PCIX_COMMAND 0x62
+#define POWAR_EN 0x80000000
+#define POWAR_IO_READ 0x00080000
+#define POWAR_MEM_READ 0x00040000
+#define POWAR_IO_WRITE 0x00008000
+#define POWAR_MEM_WRITE 0x00004000
+#define POWAR_MEM_512M 0x0000001c
+#define POWAR_IO_1M 0x00000013
+
+#define PIWAR_EN 0x80000000
+#define PIWAR_PF 0x20000000
+#define PIWAR_LOCAL 0x00f00000
+#define PIWAR_READ_SNOOP 0x00050000
+#define PIWAR_WRITE_SNOOP 0x00005000
+#define PIWAR_MEM_2G 0x0000001e
-/* L2 Cache Registers(0x2_0000-0x2_1000) */
+/*
+ * L2 Cache Registers(0x2_0000-0x2_1000)
+ */
typedef struct ccsr_l2cache {
uint l2ctl; /* 0x20000 - L2 configuration register 0 */
char res1[12];
char res15[420];
} ccsr_l2cache_t;
-
-/* DMA Registers(0x2_1000-0x2_2000) */
-
+/*
+ * DMA Registers(0x2_1000-0x2_2000)
+ */
typedef struct ccsr_dma {
char res1[256];
uint mr0; /* 0x21100 - DMA 0 Mode Register */
char res22[11516];
} ccsr_dma_t;
-/* tsec1 tsec2: 24000-26000 */
+/*
+ * tsec1 tsec2: 24000-26000
+ */
typedef struct ccsr_tsec {
char res1[16];
uint ievent; /* 0x24010 - Interrupt Event Register */
char res74[1024];
} ccsr_tsec_t;
-/* PIC Registers(0x2_6000-0x4_0000-0x8_0000) */
-
+/*
+ * PIC Registers(0x4_0000-0x8_0000)
+ */
typedef struct ccsr_pic {
- char res0[106496]; /* 0x26000-0x40000 */
- char res1[64];
+ char res1[64]; /* 0x40000 */
uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
char res2[12];
uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
uint frr; /* 0x41000 - Feature Reporting Register */
char res10[28];
uint gcr; /* 0x41020 - Global Configuration Register */
+#define MPC85xx_PICGCR_RST 0x80000000
+#define MPC85xx_PICGCR_M 0x20000000
char res11[92];
uint vir; /* 0x41080 - Vendor Identification Register */
char res12[12];
char res150[130892];
} ccsr_pic_t;
-/* CPM Block(0x8_0000-0xc_0000) */
-#if defined(CONFIG_MPC8540) \
- || defined(CONFIG_MPC8541) \
- || defined(CONFIG_MPC8555)
+/*
+ * CPM Block(0x8_0000-0xc_0000)
+ */
+#ifndef CONFIG_CPM2
typedef struct ccsr_cpm {
char res[262144];
} ccsr_cpm_t;
#else
-/* 0x8000-0x8ffff:DPARM */
-
-/* 0x9000-0x90bff: General SIU */
+/*
+ * 0x8000-0x8ffff:DPARM
+ * 0x9000-0x90bff: General SIU
+ */
typedef struct ccsr_cpm_siu {
- char res1[80];
+ char res1[80];
uint smaer;
uint smser;
uint smevr;
/* 0x91018-0x912ff: SDMA */
typedef struct ccsr_cpm_sdma {
uchar sdsr;
- char res1[3];
- uchar sdmr;
- char res2[739];
+ char res1[3];
+ uchar sdmr;
+ char res2[739];
} ccsr_cpm_sdma_t;
/* 0x91300-0x9131f: FCC1 */
/* 0x91400-0x915ef: TC layers */
typedef struct ccsr_cpm_tmp1 {
- char res[496];
+ char res[496];
} ccsr_cpm_tmp1_t;
/* 0x915f0-0x9185f: BRGs:5,6,7,8 */
/* 0x91a80-0x91a9f */
typedef struct ccsr_cpm_tmp2 {
- char res[32];
+ char res[32];
} ccsr_cpm_tmp2_t;
/* 0x91aa0-0x91aff: SPI */
/* Some references are into the unique and known dpram spaces,
* others are from the generic base.
*/
-#define im_dprambase im_dpram1
- u_char im_dpram1[16*1024];
- char res1[16*1024];
- u_char im_dpram2[16*1024];
- char res2[16*1024];
-
- ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
- ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */
- ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
- ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
- ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
+#define im_dprambase im_dpram1
+ u_char im_dpram1[16*1024];
+ char res1[16*1024];
+ u_char im_dpram2[16*1024];
+ char res2[16*1024];
+ ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
+ ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */
+ ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
+ ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
+ ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
ccsr_cpm_fcc1_t im_cpm_fcc1;
ccsr_cpm_fcc2_t im_cpm_fcc2;
ccsr_cpm_fcc3_t im_cpm_fcc3;
ccsr_cpm_iram_t im_cpm_iram;
} ccsr_cpm_t;
#endif
-/* RapidIO Registers(0xc_0000-0xe_0000) */
+/*
+ * RapidIO Registers(0xc_0000-0xe_0000)
+ */
typedef struct ccsr_rio {
uint didcar; /* 0xc0000 - Device Identity Capability Register */
uint dicar; /* 0xc0004 - Device Information Capability Register */
char res58[60176];
} ccsr_rio_t;
-/* Global Utilities Register Block(0xe_0000-0xf_ffff) */
+/* Quick Engine Block Pin Muxing Registers (0xe_0100 - 0xe_01bf) */
+typedef struct par_io {
+ uint cpodr; /* 0x100 */
+ uint cpdat; /* 0x104 */
+ uint cpdir1; /* 0x108 */
+ uint cpdir2; /* 0x10c */
+ uint cppar1; /* 0x110 */
+ uint cppar2; /* 0x114 */
+ char res[8];
+}par_io_t;
+
+/*
+ * Global Utilities Register Block(0xe_0000-0xf_ffff)
+ */
typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
uint porbmsr; /* 0xe0004 - POR boot mode status register */
+#define MPC85xx_PORBMSR_HA 0x00070000
uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
+#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
+#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
+#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
+#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
+#define MPC85xx_PORDEVSR_IO_SEL 0x00380000
+#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
+#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
+#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
+#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
+#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
+#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
+#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
+#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
- char res1[12];
+ uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */
+#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000020
+ char res1[8];
uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
char res2[12];
uint gpiocr; /* 0xe0030 - GPIO control register */
uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
char res6[12];
uint devdisr; /* 0xe0070 - Device disable control */
+#define MPC85xx_DEVDISR_PCI1 0x80000000
+#define MPC85xx_DEVDISR_PCI2 0x40000000
+#define MPC85xx_DEVDISR_PCIE 0x20000000
+#define MPC85xx_DEVDISR_LBC 0x08000000
+#define MPC85xx_DEVDISR_PCIE2 0x04000000
+#define MPC85xx_DEVDISR_PCIE3 0x02000000
+#define MPC85xx_DEVDISR_SEC 0x01000000
+#define MPC85xx_DEVDISR_SRIO 0x00080000
+#define MPC85xx_DEVDISR_RMSG 0x00040000
+#define MPC85xx_DEVDISR_DDR 0x00010000
+#define MPC85xx_DEVDISR_CPU 0x00008000
+#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
+#define MPC85xx_DEVDISR_TB 0x00004000
+#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
+#define MPC85xx_DEVDISR_CPU1 0x00002000
+#define MPC85xx_DEVDISR_TB1 0x00001000
+#define MPC85xx_DEVDISR_DMA 0x00000400
+#define MPC85xx_DEVDISR_TSEC1 0x00000080
+#define MPC85xx_DEVDISR_TSEC2 0x00000040
+#define MPC85xx_DEVDISR_TSEC3 0x00000020
+#define MPC85xx_DEVDISR_TSEC4 0x00000010
+#define MPC85xx_DEVDISR_I2C 0x00000004
+#define MPC85xx_DEVDISR_DUART 0x00000002
char res7[12];
uint powmgtcsr; /* 0xe0080 - Power management status and control register */
char res8[12];
char res9[12];
uint pvr; /* 0xe00a0 - Processor version register */
uint svr; /* 0xe00a4 - System version register */
- char res10[3416];
+ char res10a[8];
+ uint rstcr; /* 0xe00b0 - Reset control register */
+#ifdef CONFIG_MPC8568
+ char res10b[76];
+ par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */
+ char res10c[3136];
+#else
+ char res10b[3404];
+#endif
uint clkocr; /* 0xe0e00 - Clock out select register */
char res11[12];
uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
char res12[12];
uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
- char res13[61915];
+ char res13[248];
+ uint lbiuiplldcr0; /* 0xe0f1c -- LBIU PLL Debug Reg 0 */
+ uint lbiuiplldcr1; /* 0xe0f20 -- LBIU PLL Debug Reg 1 */
+ uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */
+ uint res14; /* 0xe0f28 */
+ uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */
+ char res15[61648]; /* 0xe0f30 to 0xefffff */
} ccsr_gur_t;
-typedef struct immap {
- ccsr_local_ecm_t im_local_ecm;
- ccsr_ddr_t im_ddr;
- ccsr_i2c_t im_i2c;
- ccsr_duart_t im_duart;
- ccsr_lbc_t im_lbc;
- ccsr_pcix_t im_pcix;
- ccsr_l2cache_t im_l2cache;
- ccsr_dma_t im_dma;
- ccsr_tsec_t im_tsec1;
- ccsr_tsec_t im_tsec2;
- ccsr_pic_t im_pic;
- ccsr_cpm_t im_cpm;
- ccsr_rio_t im_rio;
- ccsr_gur_t im_gur;
-} immap_t;
+#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
-extern immap_t *immr;
+#define CFG_MPC85xx_GUTS_OFFSET (0xE0000)
+#define CFG_MPC85xx_GUTS_ADDR (CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET)
+#define CFG_MPC85xx_ECM_OFFSET (0x0000)
+#define CFG_MPC85xx_ECM_ADDR (CFG_IMMR + CFG_MPC85xx_ECM_OFFSET)
+#define CFG_MPC85xx_DDR_OFFSET (0x2000)
+#define CFG_MPC85xx_DDR_ADDR (CFG_IMMR + CFG_MPC85xx_DDR_OFFSET)
+#define CFG_MPC85xx_DDR2_OFFSET (0x6000)
+#define CFG_MPC85xx_DDR2_ADDR (CFG_IMMR + CFG_MPC85xx_DDR2_OFFSET)
+#define CFG_MPC85xx_LBC_OFFSET (0x5000)
+#define CFG_MPC85xx_LBC_ADDR (CFG_IMMR + CFG_MPC85xx_LBC_OFFSET)
+#define CFG_MPC85xx_PCIX_OFFSET (0x8000)
+#define CFG_MPC85xx_PCIX_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX_OFFSET)
+#define CFG_MPC85xx_PCIX2_OFFSET (0x9000)
+#define CFG_MPC85xx_PCIX2_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX2_OFFSET)
+#define CFG_MPC85xx_L2_OFFSET (0x20000)
+#define CFG_MPC85xx_L2_ADDR (CFG_IMMR + CFG_MPC85xx_L2_OFFSET)
+#define CFG_MPC85xx_DMA_OFFSET (0x21000)
+#define CFG_MPC85xx_DMA_ADDR (CFG_IMMR + CFG_MPC85xx_DMA_OFFSET)
+#define CFG_MPC85xx_PIC_OFFSET (0x40000)
+#define CFG_MPC85xx_PIC_ADDR (CFG_IMMR + CFG_MPC85xx_PIC_OFFSET)
+#define CFG_MPC85xx_CPM_OFFSET (0x80000)
+#define CFG_MPC85xx_CPM_ADDR (CFG_IMMR + CFG_MPC85xx_CPM_OFFSET)
#endif /*__IMMAP_85xx__*/