immap_85xx: add porpllsr's plat ratio definition

[u-boot] / include / asm-ppc / immap_85xx.h

diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 0efef0521437ce4ab0e67d7074929fdce4bcea3a..39fdb8e94f4cb6b427c4a7f5c6d2d2d3c2665192 100644 (file)
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -132,7 +132,7 @@ typedef struct ccsr_ddr {
        char    reg8_1a[8];
        uint    ddr_zq_cntl;            /* 0x2170 - DDR ZQ calibration control*/
        uint    ddr_wrlvl_cntl;         /* 0x2174 - DDR write leveling control*/
-       uint    ddr_pd_cntl;            /* 0x2178 - DDR pre-drive conditioning control*/
+       char    reg8_1aa[4];
        uint    ddr_sr_cntr;            /* 0x217C - DDR self refresh counter */
        uint    ddr_sdram_rcw_1;        /* 0x2180 - DDR Register Control Words 1 */
        uint    ddr_sdram_rcw_2;        /* 0x2184 - DDR Register Control Words 2 */
@@ -411,6 +411,11 @@ typedef struct ccsr_l2cache {
        char    res15[420];
 } ccsr_l2cache_t;
 
+#define MPC85xx_L2CTL_L2E                      0x80000000
+#define MPC85xx_L2CTL_L2SRAM_ENTIRE            0x00010000
+#define MPC85xx_L2ERRDIS_MBECC                 0x00000008
+#define MPC85xx_L2ERRDIS_SBECC                 0x00000004
+
 /*
  * DMA Registers(0x2_1000-0x2_2000)
  */
@@ -1537,6 +1542,8 @@ typedef struct ccsr_gur {
 #endif
 #define MPC85xx_PORPLLSR_QE_RATIO      0x3e000000
 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT                25
+#define MPC85xx_PORPLLSR_PLAT_RATIO    0x0000003e
+#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT       1
        uint    porbmsr;        /* 0xe0004 - POR boot mode status register */
 #define MPC85xx_PORBMSR_HA             0x00070000
 #define MPC85xx_PORBMSR_HA_SHIFT       16