Merge branch 'master' of git://git.denx.de/u-boot-arm

[u-boot] / include / asm-ppc / immap_85xx.h

diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index e5046bef3217624336838ad10f6a1f8747df11cd..d3c6b86d2b179b3f1f1d9b4abc6241bdf03e8e97 100644 (file)
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -58,7 +58,23 @@ typedef struct ccsr_local_ecm {
        uint    lawbar7;        /* 0xce8 - Local Access Window 7 Base Address Register */
        char    res19[4];
        uint    lawar7;         /* 0xcf0 - Local Access Window 7 Attributes Register */
-       char    res20[780];     /* XXX: LAW 8, LAW9 for 8572 */
+       char    res19_8a[20];
+       uint    lawbar8;        /* 0xd08 - Local Access Window 8 Base Address Register */
+       char    res19_8b[4];
+       uint    lawar8;         /* 0xd10 - Local Access Window 8 Attributes Register */
+       char    res19_9a[20];
+       uint    lawbar9;        /* 0xd28 - Local Access Window 9 Base Address Register */
+       char    res19_9b[4];
+       uint    lawar9;         /* 0xd30 - Local Access Window 9 Attributes Register */
+       char    res19_10a[20];
+       uint    lawbar10;       /* 0xd48 - Local Access Window 10 Base Address Register */
+       char    res19_10b[4];
+       uint    lawar10;        /* 0xd50 - Local Access Window 10 Attributes Register */
+       char    res19_11a[20];
+       uint    lawbar11;       /* 0xd68 - Local Access Window 11 Base Address Register */
+       char    res19_11b[4];
+       uint    lawar11;        /* 0xd70 - Local Access Window 11 Attributes Register */
+       char    res20[652];
        uint    eebacr;         /* 0x1000 - ECM CCB Address Configuration Register */
        char    res21[12];
        uint    eebpcr;         /* 0x1010 - ECM CCB Port Configuration Register */
@@ -119,7 +135,12 @@ typedef struct ccsr_ddr {
        uint    ddr_sr_cntr;            /* 0x217C - DDR self refresh counter */
        uint    ddr_sdram_rcw_1;        /* 0x2180 - DDR Register Control Words 1 */
        uint    ddr_sdram_rcw_2;        /* 0x2184 - DDR Register Control Words 2 */
-       char    res8_1b[2672];
+       char    res8_1b[2456];
+       uint    ddr_dsr1;               /* 0x2B20 - DDR Debug Status Register 1 */
+       uint    ddr_dsr2;               /* 0x2B24 - DDR Debug Status Register 2 */
+       uint    ddr_cdr1;               /* 0x2B28 - DDR Control Driver Register 1 */
+       uint    ddr_cdr2;               /* 0x2B2C - DDR Control Driver Register 2 */
+       char    res8_1c[200];
        uint    ip_rev1;                /* 0x2BF8 - DDR IP Block Revision 1 */
        uint    ip_rev2;                /* 0x2BFC - DDR IP Block Revision 2 */
        char    res8_2[512];
@@ -236,6 +257,21 @@ typedef struct ccsr_lbc {
        char    res8[3880];
 } ccsr_lbc_t;
 
+/*
+ * eSPI Registers(0x7000-0x8000)
+ */
+typedef struct ccsr_espi {
+       uint    mode;           /* 0x00 - eSPI mode register  */
+       uint    event;          /* 0x04 - eSPI event register */
+       uint    mask;           /* 0x08 - eSPI mask register  */
+       uint    com;            /* 0x0c - eSPI command register */
+       uint    tx;             /* 0x10 - eSPI transmit FIFO access register */
+       uint    rx;             /* 0x14 - eSPI receive FIFO access register */
+       char    res1[8];        /* reserved */
+       uint    csmode[4];      /* 0x20 - 0x2c: sSPI CS0/1/2/3 mode register */
+       char    res2[4048];     /* fill up to 0x1000 */
+} ccsr_espi_t;
+
 /*
  * PCI Registers(0x8000-0x9000)
  */
@@ -1588,11 +1624,25 @@ typedef struct ccsr_gur {
        char    res2[12];
        uint    gpiocr;         /* 0xe0030 - GPIO control register */
        char    res3[12];
+#if defined(CONFIG_MPC8569)
+       uint    plppar1;
+                       /* 0xe0040 - Platform port pin assignment register 1 */
+       uint    plppar2;
+                       /* 0xe0044 - Platform port pin assignment register 2 */
+       uint    plpdir1;
+                       /* 0xe0048 - Platform port pin direction register 1 */
+       uint    plpdir2;
+                       /* 0xe004c - Platform port pin direction register 2 */
+#else
        uint    gpoutdr;        /* 0xe0040 - General-purpose output data register */
        char    res4[12];
+#endif
        uint    gpindr;         /* 0xe0050 - General-purpose input data register */
        char    res5[12];
        uint    pmuxcr;         /* 0xe0060 - Alternate function signal multiplex control */
+#define MPC85xx_PMUXCR_SD_DATA         0x80000000
+#define MPC85xx_PMUXCR_SDHC_CD         0x40000000
+#define MPC85xx_PMUXCR_SDHC_WP         0x20000000
        char    res6[12];
        uint    devdisr;        /* 0xe0070 - Device disable control */
 #define MPC85xx_DEVDISR_PCI1           0x80000000
@@ -1627,7 +1677,7 @@ typedef struct ccsr_gur {
        uint    svr;            /* 0xe00a4 - System version register */
        char    res10a[8];
        uint    rstcr;          /* 0xe00b0 - Reset control register */
-#ifdef CONFIG_MPC8568
+#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
        char    res10b[76];
        par_io_t qe_par_io[7];  /* 0xe0100 - 0xe01bf */
        char    res10c[3136];
@@ -1643,7 +1693,7 @@ typedef struct ccsr_gur {
        uint    lbiuiplldcr0;   /* 0xe0f1c -- LBIU PLL Debug Reg 0 */
        uint    lbiuiplldcr1;   /* 0xe0f20 -- LBIU PLL Debug Reg 1 */
        uint    ddrioovcr;      /* 0xe0f24 - DDR IO Override Control */
-       uint    res14;          /* 0xe0f28 */
+       uint    tsec12ioovcr;   /* 0xe0f28 - eTSEC 1/2 IO override control */
        uint    tsec34ioovcr;   /* 0xe0f2c - eTSEC 3/4 IO override control */
        char    res15[61648];   /* 0xe0f30 to 0xefffff */
 } ccsr_gur_t;
@@ -1658,6 +1708,8 @@ typedef struct ccsr_gur {
 #define CONFIG_SYS_MPC85xx_DDR2_ADDR   (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
 #define CONFIG_SYS_MPC85xx_LBC_OFFSET  (0x5000)
 #define CONFIG_SYS_MPC85xx_LBC_ADDR    (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
+#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x7000)
+#define CONFIG_SYS_MPC85xx_ESPI_ADDR   (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
 #define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000)
 #define CONFIG_SYS_MPC85xx_PCIX_ADDR   (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET        (0x9000)