ppc/85xx: Introduce low level write_tlb function

[u-boot] / include / asm-ppc / immap_85xx.h

diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index e4f5ee2bc9e9ef782d6b5292878f128218eaea23..e7d412dba234872df60cf7347d2d3c2904b401b9 100644 (file)
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -132,7 +132,7 @@ typedef struct ccsr_ddr {
        char    reg8_1a[8];
        uint    ddr_zq_cntl;            /* 0x2170 - DDR ZQ calibration control*/
        uint    ddr_wrlvl_cntl;         /* 0x2174 - DDR write leveling control*/
-       uint    ddr_pd_cntl;            /* 0x2178 - DDR pre-drive conditioning control*/
+       char    reg8_1aa[4];
        uint    ddr_sr_cntr;            /* 0x217C - DDR self refresh counter */
        uint    ddr_sdram_rcw_1;        /* 0x2180 - DDR Register Control Words 1 */
        uint    ddr_sdram_rcw_2;        /* 0x2184 - DDR Register Control Words 2 */
@@ -341,6 +341,15 @@ typedef struct ccsr_pcix {
        char    res11[476];
 } ccsr_pcix_t;
 
+typedef struct ccsr_gpio {
+       uint    gpdir;
+       uint    gpodr;
+       uint    gpdat;
+       uint    gpier;
+       uint    gpimr;
+       uint    gpicr;
+} ccsr_gpio_t;
+
 #define PCIX_COMMAND   0x62
 #define POWAR_EN       0x80000000
 #define POWAR_IO_READ  0x00080000
@@ -402,6 +411,11 @@ typedef struct ccsr_l2cache {
        char    res15[420];
 } ccsr_l2cache_t;
 
+#define MPC85xx_L2CTL_L2E                      0x80000000
+#define MPC85xx_L2CTL_L2SRAM_ENTIRE            0x00010000
+#define MPC85xx_L2ERRDIS_MBECC                 0x00000008
+#define MPC85xx_L2ERRDIS_SBECC                 0x00000004
+
 /*
  * DMA Registers(0x2_1000-0x2_2000)
  */
@@ -1530,6 +1544,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT                25
        uint    porbmsr;        /* 0xe0004 - POR boot mode status register */
 #define MPC85xx_PORBMSR_HA             0x00070000
+#define MPC85xx_PORBMSR_HA_SHIFT       16
        uint    porimpscr;      /* 0xe0008 - POR I/O impedance status and control register */
        uint    pordevsr;       /* 0xe000c - POR I/O device status regsiter */
 #define MPC85xx_PORDEVSR_SGMII1_DIS    0x20000000
@@ -1539,6 +1554,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL   0x38000000
 #define MPC85xx_PORDEVSR_PCI1          0x00800000
 #define MPC85xx_PORDEVSR_IO_SEL                0x00780000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT  19
 #define MPC85xx_PORDEVSR_PCI2_ARB      0x00040000
 #define MPC85xx_PORDEVSR_PCI1_ARB      0x00020000
 #define MPC85xx_PORDEVSR_PCI1_PCI32    0x00010000
@@ -1646,6 +1662,8 @@ typedef struct ccsr_gur {
 #define CONFIG_SYS_MPC85xx_PCIX_ADDR   (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET        (0x9000)
 #define CONFIG_SYS_MPC85xx_PCIX2_ADDR  (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
+#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0xF000)
+#define CONFIG_SYS_MPC85xx_GPIO_ADDR   (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET        (0x18000)
 #define CONFIG_SYS_MPC85xx_SATA1_ADDR  (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET        (0x19000)