* The Internal Memory Map for devices with QE on them. This
* is the superset of all QE devices (8360, etc.).
*
- * Copyright (c) 2006 Freescale Semiconductor, Inc.
+ * Copyright (c) 2006-2009 Freescale Semiconductor, Inc.
* Author: Shlomi Gridih <gridish@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
typedef struct qe_iram {
u32 iadd; /* I-RAM Address Register */
u32 idata; /* I-RAM Data Register */
- u8 res0[0x78];
+ u8 res0[0x4];
+ u32 iready;
+ u8 res1[0x70];
} __attribute__ ((packed)) qe_iram_t;
/* QE Interrupt Controller
u8 res4[0x200 - 0x091];
} __attribute__ ((packed)) ucc_slow_t;
+typedef struct ucc_mii_mng {
+ u32 miimcfg; /* MII management configuration reg */
+ u32 miimcom; /* MII management command reg */
+ u32 miimadd; /* MII management address reg */
+ u32 miimcon; /* MII management control reg */
+ u32 miimstat; /* MII management status reg */
+ u32 miimind; /* MII management indication reg */
+ u32 ifctl; /* interface control reg */
+ u32 ifstat; /* interface statux reg */
+} __attribute__ ((packed))uec_mii_t;
+
typedef struct ucc_ethernet {
u32 maccfg1; /* mac configuration reg. 1 */
u32 maccfg2; /* mac configuration reg. 2 */
u8 res2[0x48];
} __attribute__ ((packed)) dbg_t;
-/* RISC Special Registers (Trap and Breakpoint)
+/*
+ * RISC Special Registers (Trap and Breakpoint). These are described in
+ * the QE Developer's Handbook.
*/
typedef struct rsp {
- u8 fixme[0x100];
+ u32 tibcr[16]; /* Trap/instruction breakpoint control regs */
+ u8 res0[64];
+ u32 ibcr0;
+ u32 ibs0;
+ u32 ibcnr0;
+ u8 res1[4];
+ u32 ibcr1;
+ u32 ibs1;
+ u32 ibcnr1;
+ u32 npcr;
+ u32 dbcr;
+ u32 dbar;
+ u32 dbamr;
+ u32 dbsr;
+ u32 dbcnr;
+ u8 res2[12];
+ u32 dbdr_h;
+ u32 dbdr_l;
+ u32 dbdmr_h;
+ u32 dbdmr_l;
+ u32 bsr;
+ u32 bor;
+ u32 bior;
+ u8 res3[4];
+ u32 iatr[4];
+ u32 eccr; /* Exception control configuration register */
+ u32 eicr;
+ u8 res4[0x100-0xf8];
} __attribute__ ((packed)) rsp_t;
typedef struct qe_immap {
u8 res14[0x300];
u8 res15[0x3A00];
u8 res16[0x8000]; /* 0x108000 - 0x110000 */
+#if defined(CONFIG_MPC8568)
+ u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */
+ u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */
+#elif defined(CONFIG_MPC8569)
+ u8 muram[0x20000]; /* 0x1_0000 - 0x3_0000 Multi-user RAM */
+ u8 res17[0x10000]; /* 0x3_0000 - 0x4_0000 */
+#else
u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */
u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
+#endif
} __attribute__ ((packed)) qe_map_t;
extern qe_map_t *qe_immr;
+#if defined(CONFIG_MPC8568)
+#define QE_MURAM_SIZE 0x10000UL
+#elif defined(CONFIG_MPC8569)
+#define QE_MURAM_SIZE 0x20000UL
+#elif defined(CONFIG_MPC8360)
+#define QE_MURAM_SIZE 0xc000UL
+#elif defined(CONFIG_MPC832x)
+#define QE_MURAM_SIZE 0x4000UL
+#endif
+
+#if defined(CONFIG_MPC8323)
+#define MAX_QE_RISC 1
+#define QE_NUM_OF_SNUM 28
+#elif defined(CONFIG_MPC8569)
+#define MAX_QE_RISC 4
+#define QE_NUM_OF_SNUM 46
+#else
+#define MAX_QE_RISC 2
+#define QE_NUM_OF_SNUM 28
+#endif
+
#endif /* __IMMAP_QE_H__ */