esd WUH405 and DU405 board updated

[u-boot] / include / asm-ppc / mmu.h

diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 675ccddd636f4b26230ad551fb26887d34bba9b9..2606b79a2495d31463db0f642c6ead44a67dff30 100644 (file)
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -370,4 +370,104 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
 #define TLB_M           0x00000002      /* Memory is coherent */
 #define TLB_G           0x00000001      /* Memory is guarded from prefetch */
 
+/*
+ * e500 support
+ */
+
+#define MAS0_TLBSEL     0x10000000
+#define MAS0_ESEL       0x000F0000
+#define MAS0_NV         0x00000001
+
+#define MAS1_VALID      0x80000000
+#define MAS1_IPROT      0x40000000
+#define MAS1_TID        0x00FF0000
+#define MAS1_TS         0x00001000
+#define MAS1_TSIZE     0x00000F00
+
+#define MAS2_EPN        0xFFFFF000
+#define MAS2_SHAREN     0x00000200
+#define MAS2_X0         0x00000040
+#define MAS2_X1         0x00000020
+#define MAS2_W          0x00000010
+#define MAS2_I          0x00000008
+#define MAS2_M          0x00000004
+#define MAS2_G          0x00000002
+#define MAS2_E          0x00000001
+
+#define MAS3_RPN        0xFFFFF000
+#define MAS3_U0         0x00000200
+#define MAS3_U1         0x00000100
+#define MAS3_U2         0x00000080
+#define MAS3_U3         0x00000040
+#define MAS3_UX         0x00000020
+#define MAS3_SX         0x00000010
+#define MAS3_UW         0x00000008
+#define MAS3_SW         0x00000004
+#define MAS3_UR         0x00000002
+#define MAS3_SR         0x00000001
+
+#define MAS4_TLBSELD    0x10000000
+#define MAS4_TIDDSEL    0x00030000
+#define MAS4_DSHAREN    0x00001000
+#define MAS4_TSIZED(x)  (x << 8)
+#define MAS4_X0D        0x00000040
+#define MAS4_X1D        0x00000020
+#define MAS4_WD         0x00000010
+#define MAS4_ID         0x00000008
+#define MAS4_MD         0x00000004
+#define MAS4_GD         0x00000002
+#define MAS4_ED         0x00000001
+
+#define MAS6_SPID       0x00FF0000
+#define MAS6_SAS        0x00000001
+
+#define BOOKE_PAGESZ_1K         0
+#define BOOKE_PAGESZ_4K         1
+#define BOOKE_PAGESZ_16K        2
+#define BOOKE_PAGESZ_64K        3
+#define BOOKE_PAGESZ_256K       4
+#define BOOKE_PAGESZ_1M         5
+#define BOOKE_PAGESZ_4M         6
+#define BOOKE_PAGESZ_16M        7
+#define BOOKE_PAGESZ_64M        8
+#define BOOKE_PAGESZ_256M       9
+#define BOOKE_PAGESZ_1GB        10
+#define BOOKE_PAGESZ_4GB        11
+
+#define LAWBAR_BASE_ADDR       0x000FFFFF
+#define LAWAR_EN               0x80000000
+#define LAWAR_TRGT_IF          0x00F00000
+#define LAWAR_SIZE             0x0000003F
+
+#define LAWAR_TRGT_IF_PCI      0x00000000
+#define LAWAR_TRGT_IF_PCI1     0x00000000
+#define LAWAR_TRGT_IF_PCIX     0x00000000
+#define LAWAR_TRGT_IF_PCI2     0x00100000
+#define LAWAR_TRGT_IF_LBC      0x00400000
+#define LAWAR_TRGT_IF_CCSR     0x00800000
+#define LAWAR_TRGT_IF_RIO      0x00c00000
+#define LAWAR_TRGT_IF_DDR      0x00f00000
+
+#define LAWAR_SIZE_BASE                0xa
+#define LAWAR_SIZE_4K          (LAWAR_SIZE_BASE+1)
+#define LAWAR_SIZE_8K          (LAWAR_SIZE_BASE+2)
+#define LAWAR_SIZE_16K         (LAWAR_SIZE_BASE+3)
+#define LAWAR_SIZE_32K         (LAWAR_SIZE_BASE+4)
+#define LAWAR_SIZE_64K         (LAWAR_SIZE_BASE+5)
+#define LAWAR_SIZE_128K                (LAWAR_SIZE_BASE+6)
+#define LAWAR_SIZE_256K                (LAWAR_SIZE_BASE+7)
+#define LAWAR_SIZE_512K                (LAWAR_SIZE_BASE+8)
+#define LAWAR_SIZE_1M          (LAWAR_SIZE_BASE+9)
+#define LAWAR_SIZE_2M          (LAWAR_SIZE_BASE+10)
+#define LAWAR_SIZE_4M          (LAWAR_SIZE_BASE+11)
+#define LAWAR_SIZE_8M          (LAWAR_SIZE_BASE+12)
+#define LAWAR_SIZE_16M         (LAWAR_SIZE_BASE+13)
+#define LAWAR_SIZE_32M         (LAWAR_SIZE_BASE+14)
+#define LAWAR_SIZE_64M         (LAWAR_SIZE_BASE+15)
+#define LAWAR_SIZE_128M                (LAWAR_SIZE_BASE+16)
+#define LAWAR_SIZE_256M                (LAWAR_SIZE_BASE+17)
+#define LAWAR_SIZE_512M                (LAWAR_SIZE_BASE+18)
+#define LAWAR_SIZE_1G          (LAWAR_SIZE_BASE+19)
+#define LAWAR_SIZE_2G          (LAWAR_SIZE_BASE+20)
+
 #endif /* _PPC_MMU_H_ */