Merge branch 'master' of git://git.denx.de/u-boot-arm

[u-boot] / include / asm-ppc / mmu.h

diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index 050a7b6472789c9ddae318d610bd6bde169b808a..ec22a5058e1c0b2b829284246c8cf7bcec374b76 100644 (file)
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -138,6 +138,10 @@ typedef struct _MMU_context {
 extern void _tlbie(unsigned long va);  /* invalidate a TLB entry */
 extern void _tlbia(void);              /* invalidate all TLB entries */
 
+#ifdef CONFIG_ADDR_MAP
+extern void init_addr_map(void);
+#endif
+
 typedef enum {
        IBAT0 = 0, IBAT1, IBAT2, IBAT3,
        DBAT0, DBAT1, DBAT2, DBAT3,
@@ -153,25 +157,64 @@ extern void print_bats(void);
 
 #endif /* __ASSEMBLY__ */
 
-/* Block size masks */
-#define BL_128K        0x000
-#define BL_256K 0x001
-#define BL_512K 0x003
-#define BL_1M   0x007
-#define BL_2M   0x00F
-#define BL_4M   0x01F
-#define BL_8M   0x03F
-#define BL_16M  0x07F
-#define BL_32M  0x0FF
-#define BL_64M  0x1FF
-#define BL_128M 0x3FF
-#define BL_256M 0x7FF
+#define BATU_VS                 0x00000002
+#define BATU_VP                 0x00000001
+#define BATU_INVALID            0x00000000
+
+#define BATL_WRITETHROUGH       0x00000040
+#define BATL_CACHEINHIBIT       0x00000020
+#define BATL_MEMCOHERENCE      0x00000010
+#define BATL_GUARDEDSTORAGE     0x00000008
+#define BATL_NO_ACCESS         0x00000000
+
+#define BATL_PP_MSK            0x00000003
+#define BATL_PP_00             0x00000000 /* No access */
+#define BATL_PP_01             0x00000001 /* Read-only */
+#define BATL_PP_10             0x00000002 /* Read-write */
+#define BATL_PP_11             0x00000003
+
+#define BATL_PP_NO_ACCESS      BATL_PP_00
+#define BATL_PP_RO             BATL_PP_01
+#define BATL_PP_RW             BATL_PP_10
+
+/* BAT Block size values */
+#define BATU_BL_128K            0x00000000
+#define BATU_BL_256K            0x00000004
+#define BATU_BL_512K            0x0000000c
+#define BATU_BL_1M              0x0000001c
+#define BATU_BL_2M              0x0000003c
+#define BATU_BL_4M              0x0000007c
+#define BATU_BL_8M              0x000000fc
+#define BATU_BL_16M             0x000001fc
+#define BATU_BL_32M             0x000003fc
+#define BATU_BL_64M             0x000007fc
+#define BATU_BL_128M            0x00000ffc
+#define BATU_BL_256M            0x00001ffc
+
+/* Block lengths for processors that support extended block length */
+#ifdef HID0_XBSEN
+#define BATU_BL_512M            0x00003ffc
+#define BATU_BL_1G              0x00007ffc
+#define BATU_BL_2G              0x0000fffc
+#define BATU_BL_4G              0x0001fffc
+#define BATU_BL_MAX            BATU_BL_4G
+#else
+#define BATU_BL_MAX            BATU_BL_256M
+#endif
 
 /* BAT Access Protection */
 #define BPP_XX 0x00            /* No access */
 #define BPP_RX 0x01            /* Read only */
 #define BPP_RW 0x02            /* Read/write */
 
+/* Macros to get values from BATs, once data is in the BAT register format */
+#define BATU_VALID(x) (x & 0x3)
+#define BATU_VADDR(x) (x & 0xfffe0000)
+#define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000)          \
+                                    | ((x & 0x0e00ULL) << 24)  \
+                                    | ((x & 0x04ULL) << 30)))
+#define BATU_SIZE(x) (1UL << (fls((x & BATU_BL_MAX) >> 2) + 17))
+
 /* Used to set up SDR1 register */
 #define HASH_TABLE_SIZE_64K    0x00010000
 #define HASH_TABLE_SIZE_128K   0x00020000
@@ -344,8 +387,10 @@ extern void print_bats(void);
  * FSL Book-E support
  */
 
-#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
-#define MAS0_ESEL(x)   ((x << 16) & 0x0FFF0000)
+#define MAS0_TLBSEL_MSK        0x30000000
+#define MAS0_TLBSEL(x) ((x << 28) & MAS0_TLBSEL_MSK)
+#define MAS0_ESEL_MSK  0x0FFF0000
+#define MAS0_ESEL(x)   ((x << 16) & MAS0_ESEL_MSK)
 #define MAS0_NV(x)     ((x) & 0x00000FFF)
 
 #define MAS1_VALID     0x80000000
@@ -405,6 +450,8 @@ extern void print_bats(void);
                (((epn) & MAS3_RPN) | (wimge))
 #define FSL_BOOKE_MAS3(rpn, user, perms) \
                (((rpn) & MAS3_RPN) | (user) | (perms))
+#define FSL_BOOKE_MAS7(rpn) \
+               (((u64)(rpn)) >> 32)
 
 #define BOOKE_PAGESZ_1K         0
 #define BOOKE_PAGESZ_4K         1
@@ -431,21 +478,25 @@ extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
 extern void disable_tlb(u8 esel);
 extern void invalidate_tlb(u8 tlb);
 extern void init_tlbs(void);
+extern int find_tlb_idx(void *addr, u8 tlbsel);
+
+extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
+
+extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7);
 
 #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
-       { .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \
-         .wimge = _wimge, .ts = _ts, .esel = _esel, .tsize = _sz, .iprot = _iprot }
+       { .mas0 = FSL_BOOKE_MAS0(_tlb, _esel, 0), \
+         .mas1 = FSL_BOOKE_MAS1(1, _iprot, 0, _ts, _sz), \
+         .mas2 = FSL_BOOKE_MAS2(_epn, _wimge), \
+         .mas3 = FSL_BOOKE_MAS3(_rpn, 0, _perms), \
+         .mas7 = FSL_BOOKE_MAS7(_rpn), }
 
 struct fsl_e_tlb_entry {
-       u8      tlb;
-       u32     epn;
-       u64     rpn;
-       u8      perms;
-       u8      wimge;
-       u8      ts;
-       u8      esel;
-       u8      tsize;
-       u8      iprot;
+       u32     mas0;
+       u32     mas1;
+       u32     mas2;
+       u32     mas3;
+       u32     mas7;
 };
 
 extern struct fsl_e_tlb_entry tlb_table[];
@@ -453,13 +504,7 @@ extern int num_tlb_entries;
 #endif
 #endif
 
-#if defined(CONFIG_MPC86xx)
-#define LAWBAR_BASE_ADDR       0x00FFFFFF
-#define LAWAR_TRGT_IF          0x01F00000
-#else
-#define LAWBAR_BASE_ADDR       0x000FFFFF
-#define LAWAR_TRGT_IF          0x00F00000
-#endif
+#ifdef CONFIG_E300
 #define LAWAR_EN               0x80000000
 #define LAWAR_SIZE             0x0000003F
 
@@ -503,6 +548,7 @@ extern int num_tlb_entries;
 #define LAWAR_SIZE_8G          (LAWAR_SIZE_BASE+22)
 #define LAWAR_SIZE_16G         (LAWAR_SIZE_BASE+23)
 #define LAWAR_SIZE_32G         (LAWAR_SIZE_BASE+24)
+#endif
 
 #ifdef CONFIG_440
 /* General */