/*
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
*
- * (C) Copyright 2008
+ * (C) Copyright 2008-2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
/*
* Define the number of UIC's
*/
-#if defined(CONFIG_440SPE) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_460SX)
#define UIC_MAX 4
-#elif defined(CONFIG_440GX) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#define UIC_MAX 3
#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
#define UIC_MAX 1
#endif
+#define IRQ_MAX (UIC_MAX * 32)
+
/*
* UIC register
*/
#define UIC_VR 0x7 /* UIC vector */
#define UIC_VCR 0x8 /* UIC vector configuration */
-#define UIC0_DCR_BASE 0xc0
-#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
-#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
-#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
-#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
-#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
-#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
-#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
-#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
-
-#define UIC1_DCR_BASE 0xd0
-#define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */
-#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */
-#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */
-#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
-#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
-#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
-#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
-#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
-
+/*
+ * On 440GX we use the UICB0 as UIC0. Its the root UIC where all other UIC's
+ * are cascaded on. With this trick we can use the common UIC code for 440GX
+ * too.
+ */
#if defined(CONFIG_440GX)
-#define UIC2_DCR_BASE 0x210
+#define UIC0_DCR_BASE 0x200
+#define UIC1_DCR_BASE 0xc0
+#define UIC2_DCR_BASE 0xd0
+#define UIC3_DCR_BASE 0x210
#else
+#define UIC0_DCR_BASE 0xc0
+#define UIC1_DCR_BASE 0xd0
#define UIC2_DCR_BASE 0xe0
+#define UIC3_DCR_BASE 0xf0
#endif
-#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
-#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */
-#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
-#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
-#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
-#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
-#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
-#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
-#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
-#define UIC3_DCR_BASE 0xf0
-#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
-#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */
-#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */
-#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */
-#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
-#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
-#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
-#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */
-#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
+#define UIC0SR (UIC0_DCR_BASE+0x0) /* UIC0 status */
+#define UIC0ER (UIC0_DCR_BASE+0x2) /* UIC0 enable */
+#define UIC0CR (UIC0_DCR_BASE+0x3) /* UIC0 critical */
+#define UIC0PR (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
+#define UIC0TR (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
+#define UIC0MSR (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
+#define UIC0VR (UIC0_DCR_BASE+0x7) /* UIC0 vector */
+#define UIC0VCR (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
-#if defined(CONFIG_440GX)
-#define UIC_DCR_BASE 0x200
-#define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */
-#define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */
-#define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */
-#define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */
-#define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */
-#define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */
-#define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */
-#define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration*/
-#endif /* CONFIG_440GX */
+#define UIC1SR (UIC1_DCR_BASE+0x0) /* UIC1 status */
+#define UIC1ER (UIC1_DCR_BASE+0x2) /* UIC1 enable */
+#define UIC1CR (UIC1_DCR_BASE+0x3) /* UIC1 critical */
+#define UIC1PR (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
+#define UIC1TR (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
+#define UIC1MSR (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
+#define UIC1VR (UIC1_DCR_BASE+0x7) /* UIC1 vector */
+#define UIC1VCR (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
+
+#define UIC2SR (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
+#define UIC2ER (UIC2_DCR_BASE+0x2) /* UIC2 enable */
+#define UIC2CR (UIC2_DCR_BASE+0x3) /* UIC2 critical */
+#define UIC2PR (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
+#define UIC2TR (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
+#define UIC2MSR (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
+#define UIC2VR (UIC2_DCR_BASE+0x7) /* UIC2 vector */
+#define UIC2VCR (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
-/* The following is for compatibility with 405 code */
-#define uicsr uic0sr
-#define uicer uic0er
-#define uiccr uic0cr
-#define uicpr uic0pr
-#define uictr uic0tr
-#define uicmsr uic0msr
-#define uicvr uic0vr
-#define uicvcr uic0vcr
+#define UIC3SR (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
+#define UIC3ER (UIC3_DCR_BASE+0x2) /* UIC3 enable */
+#define UIC3CR (UIC3_DCR_BASE+0x3) /* UIC3 critical */
+#define UIC3PR (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
+#define UIC3TR (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
+#define UIC3MSR (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
+#define UIC3VR (UIC3_DCR_BASE+0x7) /* UIC3 vector */
+#define UIC3VCR (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
/*
* Now the interrupt vector definitions. They are different for most of
#endif /* CONFIG_440GP */
#if defined(CONFIG_440GX)
-/* UIC 0 */
-#define VECNUM_MAL_TXEOB 10
-#define VECNUM_MAL_RXEOB 11
+/* UICB 0 (440GX only) */
+/*
+ * All those defines below are off-by-one, so that the common UIC code
+ * can be used. So VECNUM_UIC1CI refers to VECNUM_UIC0CI etc.
+ */
+#define VECNUM_UIC1CI 0
+#define VECNUM_UIC1NCI 1
+#define VECNUM_UIC2CI 2
+#define VECNUM_UIC2NCI 3
+#define VECNUM_UIC3CI 4
+#define VECNUM_UIC3NCI 5
-/* UIC 1 */
-#define VECNUM_MAL_SERR (32 + 0)
-#define VECNUM_MAL_TXDE (32 + 1)
-#define VECNUM_MAL_RXDE (32 + 2)
-#define VECNUM_ETH0 (32 + 28)
-#define VECNUM_ETH1_OFFS 2
+/* UIC 0, used as UIC1 on 440GX because of UICB0 */
+#define VECNUM_MAL_TXEOB (32 + 10)
+#define VECNUM_MAL_RXEOB (32 + 11)
-/* UICB 0 (440GX only) */
-#define VECNUM_UIC0CI 0
-#define VECNUM_UIC0NCI 1
-#define VECNUM_UIC1CI 2
-#define VECNUM_UIC1NCI 3
-#define VECNUM_UIC2CI 4
-#define VECNUM_UIC2NCI 5
+/* UIC 1, used as UIC2 on 440GX because of UICB0 */
+#define VECNUM_MAL_SERR (64 + 0)
+#define VECNUM_MAL_TXDE (64 + 1)
+#define VECNUM_MAL_RXDE (64 + 2)
+#define VECNUM_ETH0 (64 + 28)
+#define VECNUM_ETH1_OFFS 2
#endif /* CONFIG_440GX */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define VECNUM_ETH1_OFFS 1
#endif /* CONFIG_460EX */
+#if defined(CONFIG_460SX)
+/* UIC 0 */
+#define VECNUM_UIC2NCI 10
+#define VECNUM_UIC2CI 11
+#define VECNUM_UIC3NCI 16
+#define VECNUM_UIC3CI 17
+#define VECNUM_ETH0 19
+#define VECNUM_ETH1_OFFS 1
+#define VECNUM_UIC1NCI 30
+#define VECNUM_UIC1CI 31
+
+/* UIC 1 */
+#define VECNUM_MAL_SERR (32 + 1)
+#define VECNUM_MAL_TXDE (32 + 2)
+#define VECNUM_MAL_RXDE (32 + 3)
+#define VECNUM_MAL_TXEOB (32 + 6)
+#define VECNUM_MAL_RXEOB (32 + 7)
+#endif /* CONFIG_460EX */
+
#if !defined(VECNUM_ETH1_OFFS)
#define VECNUM_ETH1_OFFS 1
#endif
* Mask definitions (used for example in 4xx_enet.c)
*/
#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f))
+/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */
#define UIC_NR(vec) ((vec) >> 5)
#endif /* _PPC4xx_UIC_H_ */
projects / u-boot / blobdiff