Merge with rsync://git-user@source.denx.net/git/u-boot.git

[u-boot] / include / asm-ppc / processor.h

diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 20949dcc3973e666d0a08ee5ff3c44438e9ac3a7..6b131b6b08a7b8c42fb88a0d92f323fd31f1623e 100644 (file)
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -200,6 +200,11 @@
 #define SPRN_HASH1     0x3D2   /* Primary Hash Address Register */
 #define SPRN_HASH2     0x3D3   /* Secondary Hash Address Resgister */
 #define SPRN_HID0      0x3F0   /* Hardware Implementation Register 0 */
+
+#define HID0_ICE_SHIFT         15
+#define HID0_DCE_SHIFT         14
+#define HID0_DLOCK_SHIFT       12
+
 #define   HID0_EMCP    (1<<31)         /* Enable Machine Check pin */
 #define   HID0_EBA     (1<<29)         /* Enable Bus Address Parity */
 #define   HID0_EBD     (1<<28)         /* Enable Bus Data Parity */
@@ -211,10 +216,10 @@
 #define   HID0_NAP     (1<<22)
 #define   HID0_SLEEP   (1<<21)
 #define   HID0_DPM     (1<<20)
-#define   HID0_ICE     (1<<15)         /* Instruction Cache Enable */
-#define   HID0_DCE     (1<<14)         /* Data Cache Enable */
+#define   HID0_ICE     (1<<HID0_ICE_SHIFT)     /* Instruction Cache Enable */
+#define   HID0_DCE     (1<<HID0_DCE_SHIFT)     /* Data Cache Enable */
 #define   HID0_ILOCK   (1<<13)         /* Instruction Cache Lock */
-#define   HID0_DLOCK   (1<<12)         /* Data Cache Lock */
+#define   HID0_DLOCK   (1<<HID0_DLOCK_SHIFT)   /* Data Cache Lock */
 #define   HID0_ICFI    (1<<11)         /* Instr. Cache Flash Invalidate */
 #define   HID0_DCFI    (1<<10)         /* Data Cache Flash Invalidate */
 #define   HID0_DCI     HID0_DCFI
@@ -718,6 +723,8 @@
 #define PVR_405GPR_RB  0x50910951
 #define PVR_440GP_RB   0x40120440
 #define PVR_440GP_RC   0x40120481
+#define PVR_440EP_RA   0x42221850
+#define PVR_440EP_RB   0x422218D3
 #define PVR_440GX_RA   0x51B21850
 #define PVR_440GX_RB   0x51B21851
 #define PVR_440GX_RC   0x51B21892