Merge branch 'mpc86xx'

[u-boot] / include / asm-ppc / processor.h

diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 6b131b6b08a7b8c42fb88a0d92f323fd31f1623e..6e1d610c13081380c864de1583f6dc34ca8b8167 100644 (file)
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -264,6 +264,7 @@
 #define SPRN_ICTC      0x3FB   /* Instruction Cache Throttling Control Reg */
 #define SPRN_IMISS     0x3D4   /* Instruction TLB Miss Register */
 #define SPRN_IMMR      0x27E   /* Internal Memory Map Register */
+#define SPRN_LDSTCR    0x3F8   /* Load/Store Control Register */
 #define SPRN_L2CR      0x3F9   /* Level 2 Cache Control Regsiter */
 #define SPRN_LR                0x008   /* Link Register */
 #define SPRN_MBAR       0x137   /* System memory base address */
@@ -310,10 +311,10 @@
 #define SPRN_TBHU      0x3CC   /* Time Base High User-mode */
 #define SPRN_TBLO      0x3DD   /* Time Base Low */
 #define SPRN_TBLU      0x3CD   /* Time Base Low User-mode */
-#define SPRN_TBRL      0x10D   /* Time Base Read Lower Register */
-#define SPRN_TBRU      0x10C   /* Time Base Read Upper Register */
-#define SPRN_TBWL      0x11D   /* Time Base Write Lower Register */
-#define SPRN_TBWU      0x11C   /* Time Base Write Upper Register */
+#define SPRN_TBRL      0x10C   /* Time Base Read Lower Register */
+#define SPRN_TBRU      0x10D   /* Time Base Read Upper Register */
+#define SPRN_TBWL      0x11C   /* Time Base Write Lower Register */
+#define SPRN_TBWU      0x11D   /* Time Base Write Upper Register */
 #ifndef CONFIG_BOOKE
 #define SPRN_TCR       0x3DA   /* Timer Control Register */
 #else
@@ -443,6 +444,11 @@
 #define SPRN_MCSR      0x23c   /* Machine Check Syndrome register */
 #define ESR_ST          0x00800000      /* Store Operation */
 
+#if defined(CONFIG_MPC86xx)
+#define SPRN_MSSCRO    0x3f6
+#endif
+
+
 /* Short-hand versions for a number of the above SPRNs */
 
 #define CTR    SPRN_CTR        /* Counter Register */
@@ -501,10 +507,14 @@
 #define ICMP   SPRN_ICMP       /* Instruction TLB Compare Register */
 #define IMISS  SPRN_IMISS      /* Instruction TLB Miss Register */
 #define IMMR   SPRN_IMMR       /* PPC 860/821 Internal Memory Map Register */
+#define LDSTCR SPRN_LDSTCR     /* Load/Store Control Register */
 #define L2CR   SPRN_L2CR       /* PPC 750 L2 control register */
 #define LR     SPRN_LR
 #define MBAR    SPRN_MBAR       /* System memory base address */
-#if defined(CONFIG_E500)
+#if defined(CONFIG_MPC86xx)
+#define MSSCR0 SPRN_MSSCRO
+#endif
+#if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 #define PIR    SPRN_PIR
 #endif
 #define SVR    SPRN_SVR        /* System-On-Chip Version Register */
@@ -538,7 +548,7 @@
 #define CSRR0  SPRN_CSRR0
 #define CSRR1  SPRN_CSRR1
 #define IVPR   SPRN_IVPR
-#define USPRG0 SPRN_USPRG0
+#define USPRG0 SPRN_USPRG
 #define SPRG4R SPRN_SPRG4R
 #define SPRG5R SPRN_SPRG5R
 #define SPRG6R SPRN_SPRG6R
@@ -694,7 +704,7 @@
 #define PVR_REV(pvr)  (((pvr) >>   0) & 0xFFFF)        /* Revison field */
 
 /*
- * IBM has further subdivided the standard PowerPC 16-bit version and
+ * AMCC has further subdivided the standard PowerPC 16-bit version and
  * revision subfields of the PVR for the PowerPC 403s into the following:
  */
 
@@ -724,11 +734,19 @@
 #define PVR_440GP_RB   0x40120440
 #define PVR_440GP_RC   0x40120481
 #define PVR_440EP_RA   0x42221850
-#define PVR_440EP_RB   0x422218D3
+#define PVR_440EP_RB   0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
+#define PVR_440EP_RC   0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
+#define PVR_440GR_RA   0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
+#define PVR_440GR_RB   0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
 #define PVR_440GX_RA   0x51B21850
 #define PVR_440GX_RB   0x51B21851
 #define PVR_440GX_RC   0x51B21892
+#define PVR_440GX_RF   0x51B21894
 #define PVR_405EP_RB   0x51210950
+#define PVR_440SP_RA   0x53221850
+#define PVR_440SP_RB   0x53221891
+#define PVR_440SPe_RA  0x53421890
+#define PVR_440SPe_RB  0x53421891
 #define PVR_601                0x00010000
 #define PVR_602                0x00050000
 #define PVR_603                0x00030000
@@ -751,6 +769,8 @@
 #define PVR_85xx_REV1  (PVR_85xx | 0x0010)
 #define PVR_85xx_REV2  (PVR_85xx | 0x0020)
 
+#define PVR_86xx       0x80040000
+#define PVR_86xx_REV1  (PVR_86xx | 0x0010)
 
 /*
  * For the 8xx processors, all of them report the same PVR family for
@@ -804,6 +824,8 @@
 #define SVR_8548       0x8031
 #define SVR_8548_E     0x8039
 
+#define SVR_8641       0x8090
+#define SVR_8641D      0x8091
 
 /* I am just adding a single entry for 8260 boards.  I think we may be
  * able to combine mbx, fads, rpxlite, bseip, and classic into a single
@@ -825,7 +847,7 @@
 #define _MACH_gemini   0x00000200      /* Synergy Microsystems gemini board */
 #define _MACH_classic  0x00000400      /* RPCG RPX-Classic 8xx board */
 #define _MACH_oak      0x00000800      /* IBM "Oak" 403 eval. board */
-#define _MACH_walnut   0x00001000      /* IBM "Walnut" 405GP eval. board */
+#define _MACH_walnut   0x00001000      /* AMCC "Walnut" 405GP eval. board */
 #define _MACH_8260     0x00002000      /* Generic 8260 */
 #define _MACH_sandpoint 0x00004000     /* Motorola SPS Processor eval board */
 #define _MACH_tqm860   0x00008000      /* TQM860/L */