Merge branch 'master' of git://www.denx.de/git/u-boot-sh

[u-boot] / include / asm-ppc / processor.h

diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 9780fe15c0db45b6f9d958c0e2a6718bdcda38f0..86c5df2dbaadafcabfe539b9b35cb7f256814a01 100644 (file)
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -58,7 +58,6 @@
 #else
 #define MSR_KERNEL     MSR_ME
 #endif
-#define MSR_USER       MSR_KERNEL|MSR_PR|MSR_EE
 
 /* Floating Point Status and Control Register (FPSCR) Fields */
 
@@ -92,6 +91,11 @@
 
 /* Special Purpose Registers (SPRNs)*/
 
+/* PPC440 Architecture is BOOK-E */
+#ifdef CONFIG_440
+#define CONFIG_BOOKE
+#endif
+
 #define SPRN_CDBCR     0x3D7   /* Cache Debug Control Register */
 #define SPRN_CTR       0x009   /* Count Register */
 #define SPRN_DABR      0x3F5   /* Data Address Breakpoint Register */
@@ -218,12 +222,14 @@
 #define   HID0_DPM     (1<<20)
 #define   HID0_ICE     (1<<HID0_ICE_SHIFT)     /* Instruction Cache Enable */
 #define   HID0_DCE     (1<<HID0_DCE_SHIFT)     /* Data Cache Enable */
+#define   HID0_TBEN    (1<<14)         /* Time Base Enable */
 #define   HID0_ILOCK   (1<<13)         /* Instruction Cache Lock */
 #define   HID0_DLOCK   (1<<HID0_DLOCK_SHIFT)   /* Data Cache Lock */
 #define   HID0_ICFI    (1<<11)         /* Instr. Cache Flash Invalidate */
 #define   HID0_DCFI    (1<<10)         /* Data Cache Flash Invalidate */
 #define   HID0_DCI     HID0_DCFI
 #define   HID0_SPD     (1<<9)          /* Speculative disable */
+#define   HID0_ENMAS7  (1<<7)          /* Enable MAS7 Update for 36-bit phys */
 #define   HID0_SGE     (1<<7)          /* Store Gathering Enable */
 #define   HID0_SIED    HID_SGE         /* Serial Instr. Execution [Disable] */
 #define   HID0_DCFA    (1<<6)          /* Data Cache Flush Assist */
@@ -418,6 +424,8 @@
 #define SPRN_IVOR15    0x19f   /* Interrupt Vector Offset Register 15 */
 
 /* e500 definitions */
+#define SPRN_L1CFG0     0x203   /* L1 Cache Configuration Register 0 */
+#define SPRN_L1CFG1     0x204   /* L1 Cache Configuration Register 1 */
 #define SPRN_L1CSR0     0x3f2   /* L1 Data Cache Control and Status Register 0 */
 #define   L1CSR0_CPE            0x00010000     /* Data Cache Parity Enable */
 #define   L1CSR0_DCFI           0x00000002      /* Data Cache Flash Invalidate */
@@ -451,6 +459,7 @@
 #define SPRN_PID1       0x279   /* Process ID Register 1 */
 #define SPRN_PID2       0x27a   /* Process ID Register 2 */
 #define SPRN_MCSR      0x23c   /* Machine Check Syndrome register */
+#define SPRN_MCAR      0x23d   /* Machine Check Address register */
 #ifdef CONFIG_440
 #define MCSR_MCS       0x80000000      /* Machine Check Summary */
 #define MCSR_IB                0x40000000      /* Instruction PLB Error */
@@ -465,7 +474,8 @@
 #define ESR_ST          0x00800000      /* Store Operation */
 
 #if defined(CONFIG_MPC86xx)
-#define SPRN_MSSCRO    0x3f6
+#define SPRN_MSSCR0    0x3f6
+#define SPRN_MSSSR0    0x3f7
 #endif
 
 
@@ -532,7 +542,7 @@
 #define LR     SPRN_LR
 #define MBAR    SPRN_MBAR       /* System memory base address */
 #if defined(CONFIG_MPC86xx)
-#define MSSCR0 SPRN_MSSCRO
+#define MSSCR0 SPRN_MSSCR0
 #endif
 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 #define PIR    SPRN_PIR
@@ -613,6 +623,8 @@
 #define MCSRR1 SPRN_MCSRR1
 #define L1CSR0 SPRN_L1CSR0
 #define L1CSR1 SPRN_L1CSR1
+#define L1CFG0 SPRN_L1CFG0
+#define L1CFG1 SPRN_L1CFG1
 #define MCSR   SPRN_MCSR
 #define MMUCSR0        SPRN_MMUCSR0
 #define BUCSR  SPRN_BUCSR
@@ -628,6 +640,12 @@
 #define MAS6   SPRN_MAS6
 #define MAS7   SPRN_MAS7
 
+#if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx)
+#define DAR_DEAR DEAR
+#else
+#define DAR_DEAR DAR
+#endif
+
 /* Device Control Registers */
 
 #define DCRN_BEAR      0x090   /* Bus Error Address Register */
@@ -756,6 +774,10 @@
 #define PVR_405EP_RA   0x51210950
 #define PVR_405GPR_RB  0x50910951
 #define PVR_405EZ_RA   0x41511460
+#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A with Security */
+#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A without Security */
+#define PVR_405EX1_RA  0x12911477 /* 405EX rev A with Security */
+#define PVR_405EX2_RA  0x12911475 /* 405EX rev A without Security */
 #define PVR_440GP_RB   0x40120440
 #define PVR_440GP_RC   0x40120481
 #define PVR_440EP_RA   0x42221850
@@ -866,6 +888,7 @@
 #define SVR_8544_E     0x803C
 #define SVR_8548       0x8031
 #define SVR_8548_E     0x8039
+#define SVR_8610       0x80A0
 #define SVR_8641       0x8090
 #define SVR_8568_E     0x807D