arm: mx5: Enable CONFIG_SYS_GENERIC_BOARD on M53EVK

[u-boot] / include / commproc.h

diff --git a/include/commproc.h b/include/commproc.h
index 605aac2ec22be1d2dc38e036778a15346360f550..29a3e61e80303db9e66b5b2c9e3e8868e5ef520e 100644 (file)
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -954,41 +954,6 @@ typedef struct scc_enet {
 
 #endif /* CONFIG_QS860T */
 
-/***  RPXCLASSIC  *****************************************************/
-
-#ifdef CONFIG_RPXCLASSIC
-
-#ifdef CONFIG_FEC_ENET
-
-# define FEC_ENET                              /* use FEC for EThernet */
-# undef SCC_ENET
-
-#else  /* ! CONFIG_FEC_ENET */
-
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC1 use.
- */
-#define        PROFF_ENET      PROFF_SCC1
-#define        CPM_CR_ENET     CPM_CR_CH_SCC1
-#define        SCC_ENET        0
-#define PA_ENET_RXD    ((ushort)0x0001)
-#define PA_ENET_TXD    ((ushort)0x0002)
-#define PA_ENET_TCLK   ((ushort)0x0200)
-#define PA_ENET_RCLK   ((ushort)0x0800)
-#define PB_ENET_TENA   ((uint)0x00001000)
-#define PC_ENET_CLSN   ((ushort)0x0010)
-#define PC_ENET_RENA   ((ushort)0x0020)
-
-/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
- * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
- */
-#define SICR_ENET_MASK ((uint)0x000000ff)
-#define SICR_ENET_CLKRT        ((uint)0x0000003d)
-
-#endif /* CONFIG_FEC_ENET */
-
-#endif /* CONFIG_RPXCLASSIC */
-
 /***  RPXLITE  ********************************************************/
 
 #ifdef CONFIG_RPXLITE