/* CPM Command register.
*/
-#define CPM_CR_RST ((ushort)0x8000)
-#define CPM_CR_OPCODE ((ushort)0x0f00)
-#define CPM_CR_CHAN ((ushort)0x00f0)
-#define CPM_CR_FLG ((ushort)0x0001)
+#define CPM_CR_RST ((ushort)0x8000)
+#define CPM_CR_OPCODE ((ushort)0x0f00)
+#define CPM_CR_CHAN ((ushort)0x00f0)
+#define CPM_CR_FLG ((ushort)0x0001)
/* Some commands (there are more...later)
*/
/* Channel numbers.
*/
-#define CPM_CR_CH_SCC1 ((ushort)0x0000)
-#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
-#define CPM_CR_CH_SCC2 ((ushort)0x0004)
-#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */
-#define CPM_CR_CH_SCC3 ((ushort)0x0008)
-#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
-#define CPM_CR_CH_SCC4 ((ushort)0x000c)
-#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
+#define CPM_CR_CH_SCC1 ((ushort)0x0000)
+#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
+#define CPM_CR_CH_SCC2 ((ushort)0x0004)
+#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */
+#define CPM_CR_CH_SCC3 ((ushort)0x0008)
+#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
+#define CPM_CR_CH_SCC4 ((ushort)0x000c)
+#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
#define CPM_POST_WORD_ADDR CFG_CPM_POST_WORD_ADDR
#endif
+#ifndef CFG_CPM_BOOTCOUNT_ADDR
+#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong))
+#else
+#define CPM_BOOTCOUNT_ADDR CFG_CPM_BOOTCOUNT_ADDR
+#endif
+
#define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
/* Export the base address of the communication processor registers
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004)
-#define PA_ENET_TXD ((ushort)0x0008)
+#define PA_ENET_RXD ((ushort)0x0004)
+#define PA_ENET_TXD ((ushort)0x0008)
#define PA_ENET_TCLK ((ushort)0x0100)
#define PA_ENET_RCLK ((ushort)0x0400)
#define PB_ENET_TENA ((uint)0x00002000)
#endif /* CONFIG_PCU_E, CONFIG_CCM */
+/*** ELPT860 *********************************************************/
+
+#ifdef CONFIG_ELPT860
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC1 use.
+ */
+# define PROFF_ENET PROFF_SCC1
+# define CPM_CR_ENET CPM_CR_CH_SCC1
+# define SCC_ENET 0
+
+# define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
+# define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
+# define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
+# define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */
+
+# define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
+# define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
+# define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
+
+/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to
+ * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
+ */
+# define SICR_ENET_MASK ((uint)0x000000FF)
+# define SICR_ENET_CLKRT ((uint)0x00000025)
+#endif /* CONFIG_ELPT860 */
+
/*** ESTEEM 192E **************************************************/
#ifdef CONFIG_ESTEEM192E
/* ESTEEM192E
/*** FADS860T********************************************************/
-#if defined(CONFIG_MPC860T) && defined(CONFIG_FADS)
-/* This ENET stuff is for the MPC860TFADS with ethernet on SCC1.
+#if (defined(CONFIG_MPC860T) || defined(CONFIG_MPC866_et_al)) \
+ && defined(CONFIG_FADS)
+/* This ENET stuff is for the MPC860TFADS/MPC8xxADS with ethernet on SCC1.
*/
-
#ifdef CONFIG_SCC1_ENET
#define SCC_ENET 0
#endif /* CONFIG_SCC1_ETHERNET */
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
-#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
-#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
-#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
+#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
+#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
+#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
+#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
-#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
+#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
-#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
-#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
+#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
+#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
* SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
*/
-#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00002f00)
+#define SICR_ENET_MASK ((uint)0x0000ff00)
+#define SICR_ENET_CLKRT ((uint)0x00002f00)
#endif /* CONFIG_NX823 */
#define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */
#endif /* CONFIG_MHPC */
+/*** NETVIA *******************************************************/
+
+/* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */
+#if ( defined CONFIG_SVM_SC8xx )
+# ifndef CONFIG_FEC_ENET
+
+#define PROFF_ENET PROFF_SCC2
+#define CPM_CR_ENET CPM_CR_CH_SCC2
+#define SCC_ENET 1
+
+ /* Bits in parallel I/O port registers that have to be set/cleared
+ * * * * to configure the pins for SCC2 use.
+ * * * */
+#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
+#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
+#define PA_ENET_RCLK ((ushort)0x0400) /* PA 5 */
+#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
+
+#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
+
+#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
+#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
+ * * * * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ * * * */
+#define SICR_ENET_MASK ((uint)0x0000ff00)
+#define SICR_ENET_CLKRT ((uint)0x00003700)
+
+# else /* Use FEC for Fast Ethernet */
+
+#undef SCC_ENET
+#define FEC_ENET
+
+#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
+#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
+#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
+#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
+#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
+#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
+#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
+#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
+#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
+#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
+#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
+#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
+#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
+
+#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
+
+# endif /* CONFIG_FEC_ENET */
+#endif /* CONFIG_SVM_SC8xx */
+
+
+#if defined(CONFIG_NETVIA)
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC2 use.
+ */
+#define PROFF_ENET PROFF_SCC2
+#define CPM_CR_ENET CPM_CR_CH_SCC2
+#define SCC_ENET 1
+#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
+#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
+#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
+#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
+
+#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
+# define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */
+#elif CONFIG_NETVIA_VERSION >= 2
+# define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */
+#endif
+
+#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */
+
+#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
+#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
+
+/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
+ * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
+ */
+#define SICR_ENET_MASK ((uint)0x0000ff00)
+#define SICR_ENET_CLKRT ((uint)0x00002f00)
+
+#endif /* CONFIG_NETVIA */
+
/*** RPXCLASSIC *****************************************************/
#ifdef CONFIG_RPXCLASSIC
#define PA_ENET_TXD ((ushort)0x0008)
#define PA_ENET_TCLK ((ushort)0x0200)
#define PA_ENET_RCLK ((ushort)0x0800)
+#if defined(CONFIG_RMU)
+#define PC_ENET_TENA ((uint)0x00000002) /* PC14 */
+#else
#define PB_ENET_TENA ((uint)0x00002000)
+#endif
#define PC_ENET_CLSN ((ushort)0x0040)
#define PC_ENET_RENA ((ushort)0x0080)
#endif /* CONFIG_SXNI855T */
-/*** MVS1, TQM823L, TQM850L, ETX094, R360MPI ***********************/
+/*** MVS1, TQM823L/M, TQM850L/M, ETX094, R360MPI *******************/
#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
- defined(CONFIG_R360MPI) || \
- defined(CONFIG_TQM823L) || \
- defined(CONFIG_TQM850L) || \
- defined(CONFIG_ETX094) || \
- defined(CONFIG_RRVISION)|| \
+ defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \
+ defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \
+ defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \
+ defined(CONFIG_ETX094) || defined(CONFIG_RRVISION)|| \
(defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC2 use.
*/
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002600)
-#endif /* CONFIG_MVS v1, CONFIG_TQM823L, CONFIG_TQM850L, etc. */
+#endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
-/*** TQM860L, TQM855L ************************************************/
+/*** TQM855L/M, TQM860L/M, TQM862L/M ********************************/
-#if (defined(CONFIG_TQM860L) || defined(CONFIG_TQM855L))
+#if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \
+ defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \
+ defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M)
# ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */
#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
# endif /* CONFIG_FEC_ENET */
-#endif /* CONFIG_TQM860L, CONFIG_TQM855L */
+#endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */
-#if defined(CONFIG_NETVIA)
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC2 use.
+/*** V37 **********************************************************/
+
+#ifdef CONFIG_V37
+/* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of
+ * this may be unique to the Marel V37 configuration.
+ * Note TENA is on Port B.
*/
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
-#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
-#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
-#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
-#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
-
-#define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */
-#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */
-
-#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
-#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
+#define PA_ENET_RXD ((ushort)0x0004)
+#define PA_ENET_TXD ((ushort)0x0008)
+#define PA_ENET_TCLK ((ushort)0x0400)
+#define PA_ENET_RCLK ((ushort)0x0200)
+#define PB_ENET_TENA ((uint)0x00002000)
+#define PC_ENET_CLSN ((ushort)0x0040)
+#define PC_ENET_RENA ((ushort)0x0080)
-/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
- * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
- */
#define SICR_ENET_MASK ((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00002f00)
-
-#endif /* CONFIG_NETVIA */
+#define SICR_ENET_CLKRT ((uint)0x00002e00)
+#endif /* CONFIG_V37 */
/*********************************************************************/
* priority and SCC1 == SCCa, etc...).
*/
#define CPMVEC_NR 32
-#define CPMVEC_PIO_PC15 ((ushort)0x1f)
-#define CPMVEC_SCC1 ((ushort)0x1e)
-#define CPMVEC_SCC2 ((ushort)0x1d)
-#define CPMVEC_SCC3 ((ushort)0x1c)
-#define CPMVEC_SCC4 ((ushort)0x1b)
-#define CPMVEC_PIO_PC14 ((ushort)0x1a)
-#define CPMVEC_TIMER1 ((ushort)0x19)
-#define CPMVEC_PIO_PC13 ((ushort)0x18)
-#define CPMVEC_PIO_PC12 ((ushort)0x17)
-#define CPMVEC_SDMA_CB_ERR ((ushort)0x16)
-#define CPMVEC_IDMA1 ((ushort)0x15)
-#define CPMVEC_IDMA2 ((ushort)0x14)
-#define CPMVEC_TIMER2 ((ushort)0x12)
-#define CPMVEC_RISCTIMER ((ushort)0x11)
-#define CPMVEC_I2C ((ushort)0x10)
-#define CPMVEC_PIO_PC11 ((ushort)0x0f)
-#define CPMVEC_PIO_PC10 ((ushort)0x0e)
-#define CPMVEC_TIMER3 ((ushort)0x0c)
-#define CPMVEC_PIO_PC9 ((ushort)0x0b)
-#define CPMVEC_PIO_PC8 ((ushort)0x0a)
-#define CPMVEC_PIO_PC7 ((ushort)0x09)
-#define CPMVEC_TIMER4 ((ushort)0x07)
-#define CPMVEC_PIO_PC6 ((ushort)0x06)
-#define CPMVEC_SPI ((ushort)0x05)
-#define CPMVEC_SMC1 ((ushort)0x04)
-#define CPMVEC_SMC2 ((ushort)0x03)
-#define CPMVEC_PIO_PC5 ((ushort)0x02)
-#define CPMVEC_PIO_PC4 ((ushort)0x01)
-#define CPMVEC_ERROR ((ushort)0x00)
+#define CPMVEC_OFFSET 0x00010000
+#define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET)
+#define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET)
+#define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET)
+#define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET)
+#define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET)
+#define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET)
+#define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET)
+#define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET)
+#define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET)
+#define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET)
+#define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET)
+#define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET)
+#define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET)
+#define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET)
+#define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET)
+#define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET)
+#define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET)
+#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET)
+#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET)
extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
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