Merge branch 'next' of ../custodians into next

[u-boot] / include / configs / ATUM8548.h

diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h
index 91369a71e11342cfdcbafc0d313d964ee024dbfa..c133033bcc2b34d98a5c6b10d91002f1f5bc141f 100644 (file)
--- a/include/configs/ATUM8548.h
+++ b/include/configs/ATUM8548.h
@@ -91,9 +91,6 @@
 #define CONFIG_SYS_IMMR                CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
 
 #define PCI_SPEED              33333000        /* CPLD currenlty does not have PCI setup info */
-#define CONFIG_SYS_PCI1_ADDR   (CONFIG_SYS_CCSRBAR+0x8000)
-#define CONFIG_SYS_PCI2_ADDR   (CONFIG_SYS_CCSRBAR+0x9000)
-#define CONFIG_SYS_PCIE1_ADDR  (CONFIG_SYS_CCSRBAR+0xa000)
 
 /* DDR Setup */
 #define CONFIG_FSL_DDR2
@@ -243,27 +240,27 @@
  */
 #define CONFIG_SYS_PCI_PHYS            0x80000000      /* 1G PCI TLB */
 
-#define CONFIG_SYS_PCI1_MEM_BASE       0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS                0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00100000      /* 1M */
 
 #ifdef CONFIG_PCI2
-#define CONFIG_SYS_PCI2_MEM_BASE       0xC0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS       CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_BUS                0xC0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS       CONFIG_SYS_PCI2_MEM_BUS
 #define CONFIG_SYS_PCI2_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI2_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI2_IO_PHYS        0xe2800000
 #define CONFIG_SYS_PCI2_IO_SIZE        0x00100000      /* 1M */
 #endif
 
 #ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_MEM_BASE      0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_BUS       0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xe3000000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00100000      /*   1M */
 #endif