#define CONFIG_AMIGAONEG3SE 1
-#define CONFIG_BOARD_PRE_INIT 1
+#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R 1
#define CONFIG_VERY_BIG_RAM 1
#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=4096"
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_AMIGA_PARTITION
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DHCP | \
- CFG_CMD_ELF | \
- CFG_CMD_NET | \
- CFG_CMD_IDE | \
- CFG_CMD_FDC | \
- CFG_CMD_CACHE | \
- CFG_CMD_CONSOLE| \
- CFG_CMD_USB | \
- CFG_CMD_BSP | \
- CFG_CMD_PCI )
-
-/* CFG_CMD_MII | \ */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FDC
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CONSOLE|
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_PCI
+
#define CONFIG_PCI 1
/* #define CONFIG_PCI_SCAN_SHOW 1 */
#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
-/* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
- */
-#include <cmd_confdefs.h>
-
+#define atoi(x) simple_strtoul(x,NULL,10)
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_PROMPT "] " /* Monitor Command Prompt */
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
/* #undef CFG_HUSH_PARSER */
/* Size in bytes reserved for initial data
*/
-#define CFG_INIT_RAM_ADDR 0x400000
+/* HJF: used to be 0x400000 */
+#define CFG_INIT_RAM_ADDR 0x40000000
#define CFG_INIT_RAM_END 0x8000
#define CFG_GBL_DATA_SIZE 128
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
/* SDRAM 0 - 256MB
*/
-#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+/*HJF: #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_4M | BATU_VS | BATU_VP)
#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT0U CFG_IBAT0U*/
-/* SDRAM 1 - 256MB
+#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_DBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+/* PCI Range
*/
-#define CFG_IBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATL_PP_RW) /* | BATL_CACHEINHIBIT) */
+#define CFG_DBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+/* HJF:
+#define CFG_IBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATL_PP_RW)
#define CFG_IBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW ) /* | BATL_CACHEINHIBIT) */
+#define CFG_DBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW )
#define CFG_DBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATU_BL_256M | BATU_VS | BATU_VP)
+*/
/* Init RAM in the CPU DCache (no backing memory)
*/
#define CFG_DBAT2L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
#define CFG_DBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_IBAT2L 0 /* CFG_DBAT2L */
-#define CFG_IBAT2U 0 /* CFG_DBAT2U */
+/* This used to be commented out */
+#define CFG_IBAT2L CFG_DBAT2L
+/* This here too */
+#define CFG_IBAT2U CFG_DBAT2U
+
/* I/O and PCI memory at 0xf0000000
*/
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
#define CONFIG_3COM
/* #define CONFIG_BOOTP_RANDOM_DELAY */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE)
/*
* USB configuration
"pci_irqb_select=edge\0" \
"pci_irqc=11\0" \
"pci_irqc_select=edge\0" \
- "pci_irqd=12\0" \
+ "pci_irqd=7\0" \
"pci_irqd_select=edge\0"