Merge branch 'master' of git://git.denx.de/u-boot-marvell

[u-boot] / include / configs / BC3450.h

diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h
index f6246faeee3c28f381edfeb49a250cf8c389f2e8..a833893728180b9622ebaea6c0107d79d6fbc877 100644 (file)
--- a/include/configs/BC3450.h
+++ b/include/configs/BC3450.h
@@ -56,10 +56,17 @@
 #define CONFIG_BC3450_FP       1       /*  + enable FP O/P                 */
 #undef CONFIG_BC3450_CRT               /*  + enable CRT O/P (Debug only!)  */
 
-#define CONFIG_SYS_MPC5XXX_CLKIN       33000000 /* ... running at 33.000000MHz     */
+/*
+ * Valid values for CONFIG_SYS_TEXT_BASE are:
+ * 0xFC000000  boot low (standard configuration with room for
+ *             max 64 MByte Flash ROM)
+ * 0x00100000  boot from RAM (for testing only)
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE   0xFC000000
+#endif
 
-#define BOOTFLAG_COLD          0x01    /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM          0x02    /* Software reboot                  */
+#define CONFIG_SYS_MPC5XXX_CLKIN       33000000 /* ... running at 33.000000MHz     */
 
 #define CONFIG_HIGH_BATS       1       /* High BATs supported              */
 
@@ -377,13 +384,12 @@
 #define CONFIG_SYS_INIT_RAM_ADDR       MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-# define CONFIG_SYS_INIT_RAM_END       MPC5XXX_SRAM_POST_SIZE
+# define CONFIG_SYS_INIT_RAM_SIZE      MPC5XXX_SRAM_POST_SIZE
 #else
-# define CONFIG_SYS_INIT_RAM_END       MPC5XXX_SRAM_SIZE
+# define CONFIG_SYS_INIT_RAM_SIZE      MPC5XXX_SRAM_SIZE
 #endif /*CONFIG_POST*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE       128     /* Bytes reserved for initial data  */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE