Merge branch 'master' of rsync://rsync.denx.de/git/u-boot

[u-boot] / include / configs / CATcenter.h

diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h
index d64dd2a17ed1d5b7004c328c0ff09d6fec35ea0d..7ec4599ebb5df33c8916ce3797ddb3c00f2d6b5e 100644 (file)
--- a/include/configs/CATcenter.h
+++ b/include/configs/CATcenter.h
@@ -1,7 +1,7 @@
 /*
  * ueberarbeitet durch Christoph Seyfert
  *
- * (C) Copyright 2004 DENX Software Engineering,
+ * (C) Copyright 2004-2005 DENX Software Engineering,
  *     Wolfgang Grandegger <wg@denx.de>
  * (C) Copyright 2003
  *     DAVE Srl
@@ -110,21 +110,26 @@
 
 #define CONFIG_MII             1       /* MII PHY management           */
 #ifndef         CONFIG_EXT_PHY
-#define CONFIG_PHY_ADDR                0       /* EMAC0 PHY address            */
-#define CONFIG_PHY1_ADDR       1       /* EMAC1 PHY address            */
+#define CONFIG_PHY_ADDR                1       /* EMAC0 PHY address            */
+#define CONFIG_PHY1_ADDR       16      /* EMAC1 PHY address            */
 #else
 #define CONFIG_PHY_ADDR                2       /* PHY address                  */
 #endif
 #define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ
 
+#define        CONFIG_TIMESTAMP                /* Print image info with timestamp */
+
 #define CONFIG_COMMANDS              ( CONFIG_CMD_DFL  | \
+                               CFG_CMD_DHCP    | \
                                CFG_CMD_ELF     | \
                                CFG_CMD_EEPROM  | \
                                CFG_CMD_I2C     | \
                                CFG_CMD_IRQ     | \
                                CFG_CMD_JFFS2   | \
                                CFG_CMD_MII     | \
-                               CFG_CMD_NAND    )
+                               CFG_CMD_NAND    | \
+                               CFG_CMD_NFS     | \
+                               CFG_CMD_SNTP    )
 
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -188,6 +193,8 @@
  */
 #define CFG_NAND0_BASE 0xFF400000
 #define CFG_NAND1_BASE 0xFF000000
+#define CFG_NAND_BASE_LIST     { CFG_NAND0_BASE }
+#define NAND_BIG_DELAY_US      25
 
 /* For CATcenter there is only NAND on the module */
 #define CFG_MAX_NAND_DEVICE    1       /* Max number of NAND devices           */
@@ -213,9 +220,9 @@
 #define CFG_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
 
 
-#define NAND_DISABLE_CE(nand) do \
+#define MACRO_NAND_DISABLE_CE(nandptr) do \
 { \
-       switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+       switch((unsigned long)nandptr) \
        { \
            case CFG_NAND0_BASE: \
                out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
@@ -226,9 +233,9 @@
        } \
 } while(0)
 
-#define NAND_ENABLE_CE(nand) do \
+#define MACRO_NAND_ENABLE_CE(nandptr) do \
 { \
-       switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
+       switch((unsigned long)nandptr) \
        { \
            case CFG_NAND0_BASE: \
                out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
@@ -239,8 +246,7 @@
        } \
 } while(0)
 
-
-#define NAND_CTL_CLRALE(nandptr) do \
+#define MACRO_NAND_CTL_CLRALE(nandptr) do \
 { \
        switch((unsigned long)nandptr) \
        { \
@@ -253,7 +259,7 @@
        } \
 } while(0)
 
-#define NAND_CTL_SETALE(nandptr) do \
+#define MACRO_NAND_CTL_SETALE(nandptr) do \
 { \
        switch((unsigned long)nandptr) \
        { \
@@ -266,7 +272,7 @@
        } \
 } while(0)
 
-#define NAND_CTL_CLRCLE(nandptr) do \
+#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
 { \
        switch((unsigned long)nandptr) \
        { \
@@ -279,7 +285,7 @@
        } \
 } while(0)
 
-#define NAND_CTL_SETCLE(nandptr) do { \
+#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
        switch((unsigned long)nandptr) { \
        case CFG_NAND0_BASE: \
                out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
@@ -372,11 +378,6 @@
 
 #define CFG_FLASH_EMPTY_INFO           /* print 'E' for empty sector on flinfo */
 
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK   0       /* use for JFFS2                        */
-#define CFG_JFFS2_NUM_BANKS    1       /* ! second bank contains U-Boot        */
-#endif
-
 /*-----------------------------------------------------------------------
  * Environment Variable setup
  */
@@ -409,7 +410,7 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE                16384   /* For IBM 405 CPUs, older 405 ppc's    */
+#define CFG_DCACHE_SIZE                16384   /* For AMCC 405 CPUs, older 405 ppc's   */
                                        /* have only 8kB, 16kB is save here     */
 #define CFG_CACHELINE_SIZE     32      /* ...                  */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
@@ -762,9 +763,26 @@
 #endif /* CONFIG_NO_SERIAL_EEPROM */
 
 #define CONFIG_JFFS2_NAND 1                    /* jffs2 on nand support */
-#define CONFIG_JFFS2_NAND_DEV 0                        /* nand device jffs2 lives on */
-#define CONFIG_JFFS2_NAND_OFF 0                        /* start of jffs2 partition */
-#define CONFIG_JFFS2_NAND_SIZE 2*1024*1024     /* size of jffs2 partition */
 #define NAND_CACHE_PAGES 16                    /* size of nand cache in 512 bytes pages */
 
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV               "nand"
+#define CONFIG_JFFS2_PART_SIZE         0x00200000
+#define CONFIG_JFFS2_PART_OFFSET       0x00000000
+
+/* mtdparts command line support
+ *
+ * Note: fake mtd_id used, no linux mtd map file
+ */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT         "nand0=catcenter"
+#define MTDPARTS_DEFAULT       "mtdparts=catcenter:2m(nand)"
+*/
+
 #endif /* __CONFIG_H */