ppc4xx: Maintenance patch for esd's CPCI405 derivats

[u-boot] / include / configs / CPCI4052.h

diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index 13dbe80daf92dcc8b9f7c56dca422baeeaabb6b7..8abdbdc6df2eadc9ae920167c06feee95d304e6e 100644 (file)
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -37,6 +37,7 @@
 #define CONFIG_4xx             1       /* ...member of PPC4xx family   */
 #define CONFIG_CPCI405         1       /* ...on a CPCI405 board        */
 #define CONFIG_CPCI405_VER2    1       /* ...version 2                 */
+#undef  CONFIG_CPCI405_6U               /* enable this for 6U boards    */
 
 #define CONFIG_BOARD_EARLY_INIT_F 1    /* call board_early_init_f()    */
 
@@ -56,6 +57,10 @@
 #define CONFIG_MII             1       /* MII PHY management           */
 #define CONFIG_PHY_ADDR                0       /* PHY address                  */
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NET_MULTI       1
+#undef  CONFIG_HAS_ETH1
 
 #define CONFIG_RTC_M48T35A     1               /* ST Electronics M48 timekeeper */
 
@@ -100,6 +105,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 #undef CONFIG_WATCHDOG                 /* watchdog disabled            */
 
 #define CONFIG_SDRAM_BANK0     1       /* init onboard SDRAM bank 0    */
@@ -164,6 +171,7 @@
 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 
 #define CONFIG_PCI                     /* include pci support          */
+#define CFG_PCI_PRE_INIT                /* pci interrupt mapping etc.   */
 #define CONFIG_PCI_HOST        PCI_HOST_AUTO   /* select pci host function     */
 #define CONFIG_PCI_PNP                 /* do pci plug-and-play         */
                                        /* resource configuration       */
@@ -178,8 +186,8 @@
 #define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
+#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */