* Identify the board
*/
#if !defined(CONFIG_SC)
-#define CONFIG_IDENT_STRING " B2"
+#define CONFIG_IDENT_STRING " B2"
#else
-#define CONFIG_IDENT_STRING " SC"
+#define CONFIG_IDENT_STRING " SC"
#endif
/*
* generated by the DS1337 - and the DS1337 clock can be turned off.
*/
#if !defined(CONFIG_SC)
-#define CONFIG_8xx_GCLK_FREQ 66600000
+#define CONFIG_8xx_GCLK_FREQ 66600000
#else
-#define CONFIG_8xx_GCLK_FREQ 48000000
+#define CONFIG_8xx_GCLK_FREQ 48000000
#endif
/*
* The RS-232 console port is on SMC1
*/
#define CONFIG_8xx_CONS_SMC1
-#define CONFIG_BAUDRATE 38400
+#define CONFIG_BAUDRATE 38400
/*
* Set allowable console baud rates
*/
-#define CFG_BAUDRATE_TABLE { 9600, \
- 19200, \
- 38400, \
- 57600, \
- 115200, \
- }
+#define CFG_BAUDRATE_TABLE { 9600, \
+ 19200, \
+ 38400, \
+ 57600, \
+ 115200, \
+ }
/*
* Print console information
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp;" \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
/*
/*
* BOOTP options
*/
-#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_BOOTFILESIZE \
- )
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
/*
* The GEN860T network interface uses the on-chip 10/100 FEC with
#define CONFIG_FEC_ENET
#define CFG_DISCOVER_PHY
#define CONFIG_MII
-#define CONFIG_PHY_ADDR 0
+#define CONFIG_MII_INIT 1
+#define CONFIG_PHY_ADDR 0
/*
* Set default IP stuff just to get bootstrap entries into the
* Enable I2C and select the hardware/software driver
*/
#define CONFIG_HARD_I2C 1 /* CPM based I2C */
-#undef CONFIG_SOFT_I2C /* Bit-banged I2C */
+#undef CONFIG_SOFT_I2C /* Bit-banged I2C */
#ifdef CONFIG_HARD_I2C
#define CFG_I2C_SPEED 100000 /* clock speed in Hz */
#ifdef CONFIG_SOFT_I2C
#define PB_SCL 0x00000020 /* PB 26 */
-#define PB_SDA 0x00000010 /* PB 27 */
+#define PB_SDA 0x00000010 /* PB 27 */
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
CFG_POST_UART | \
CFG_POST_SPR )
-#ifdef CONFIG_POST
-#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
-#else
-#define CFG_CMD_POST_DIAG 0
-#endif
/*
- * List of available monitor commands. Use the system default list
- * plus add some of the "non-standard" commands back in.
- * See ./cmd_confdefs.h
- */
-#define BASE_CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_ASKENV | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_EEPROM | \
- CFG_CMD_REGINFO | \
- CFG_CMD_IMMAP | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_FPGA | \
- CFG_CMD_MII | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_POST_DIAG )
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_IMMAP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_BEDBUG
#if !defined(CONFIG_SC)
-#define CONFIG_COMMANDS ( BASE_CONFIG_COMMANDS | CFG_CMD_DOC )
-#else
-#define CONFIG_COMMANDS BASE_CONFIG_COMMANDS
+ #define CONFIG_CMD_DOC
+#endif
+
+#ifdef CONFIG_POST
+#define CONFIG_CMD_DIAG
#endif
/*
* Virtex2 FPGA configuration support
*/
#define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA CFG_XILINX_VIRTEX2
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_VIRTEX2
#define CFG_FPGA_PROG_FEEDBACK
-/************************************************************************
- * This must be included AFTER the definition of any CONFIG_COMMANDS
- */
-#include <cmd_confdefs.h>
+#define CONFIG_NAND_LEGACY
/*
* Verbose help from command monitor.
/*
* Set buffer size for console I/O
*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024
#else
#define CFG_CBSIZE 256
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
-#define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/
+#define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
* be edited if this is changed!
*/
#undef CFG_ENV_IS_IN_FLASH
-#define CFG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_IS_IN_EEPROM
-#if defined(CFG_ENV_IS_IN_EEPROM)
+#if defined(CONFIG_ENV_IS_IN_EEPROM)
#define CFG_ENV_SIZE (2 * 1024)
#define CFG_ENV_OFFSET (CFG_ENV_EEPROM_SIZE - (8 * 1024))
#else
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of above value */
#endif
*/
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR ( SYPCR_SWTC | \
- SYPCR_BMT | \
- SYPCR_BME | \
- SYPCR_SWF | \
- SYPCR_SWE | \
+ SYPCR_BMT | \
+ SYPCR_BME | \
+ SYPCR_SWF | \
+ SYPCR_SWE | \
SYPCR_SWRI | \
SYPCR_SWP \
)
#else
#define CFG_SYPCR ( SYPCR_SWTC | \
- SYPCR_BMT | \
- SYPCR_BME | \
- SYPCR_SWF | \
+ SYPCR_BMT | \
+ SYPCR_BME | \
+ SYPCR_SWF | \
SYPCR_SWP \
)
#endif
#define SCCR_MASK SCCR_EBDF11
#if !defined(CONFIG_SC)
-#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
- SCCR_COM00 | /* full strength CLKOUT */ \
- SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
- SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
+#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
+ SCCR_COM00 | /* full strength CLKOUT */ \
+ SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
+ SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
SCCR_DFNL000 | \
SCCR_DFNH000 \
)
#else
-#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
- SCCR_COM00 | /* full strength CLKOUT */ \
- SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
- SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
+#define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \
+ SCCR_COM00 | /* full strength CLKOUT */ \
+ SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \
+ SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \
SCCR_DFNL000 | \
SCCR_DFNH000 | \
SCCR_RTDIV | \
#define CFG_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \
BR_MS_GPCM | \
BR_PS_8 | \
- BR_V \
+ BR_V \
)
/*
)
#define CFG_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \
- BR_MS_UPMA | \
- BR_PS_32 | \
- BR_V \
+ BR_MS_UPMA | \
+ BR_PS_32 | \
+ BR_V \
)
/*
* MAMR settings for SDRAM
*/
#define CFG_MAMR_8COL ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \
- MAMR_PTAE | \
+ MAMR_PTAE | \
MAMR_AMA_TYPE_1 | \
- MAMR_DSA_1_CYCL | \
+ MAMR_DSA_1_CYCL | \
MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | \
MAMR_WLFA_1X | \
* 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1,
* no burst.
*/
-#define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
+#define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
OR_CSNT_SAM | \
OR_ACS_DIV2 | \
OR_BI | \
*/
#define CFG_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \
OR_SCY_15_CLK | \
- OR_BI \
+ OR_BI \
)
#define CFG_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \
BR_PS_32 | \
BR_MS_GPCM | \
- BR_V \
+ BR_V \
)
/*
* CS4* configuration for FPGA SelectMap configuration interface.
* 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge
* of GCLK1_50
*/
-#define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
+#define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \
OR_G5LS | \
OR_BI \
)
#define CFG_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \
BR_PS_8 | \
BR_MS_UPMB | \
- BR_V \
+ BR_V \
)
/*
#define CFG_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \
BR_PS_16 | \
BR_MS_GPCM | \
- BR_V \
+ BR_V \
)
/*
#endif
#endif /* __CONFIG_GEN860T_H */
-
-/* vim: set ts=4 tw=78 ai shiftwidth=4: */
projects / u-boot / blobdiff