sunxi: Fix reset hang on sun5i

[u-boot] / include / configs / HWW1U1A.h

diff --git a/include/configs/HWW1U1A.h b/include/configs/HWW1U1A.h
index 8c217562a164d239fbf0db0edc3c3bae130f1c39..6a3a11cb7f4c12b45fe2b2abca87420e00f44973 100644 (file)
--- a/include/configs/HWW1U1A.h
+++ b/include/configs/HWW1U1A.h
@@ -13,7 +13,6 @@
 /* High-level system configuration options */
 #define CONFIG_BOOKE           /* Power/PowerPC Book-E                 */
 #define CONFIG_E500            /* e500 (Power ISA v2.03 with SPE)      */
-#define CONFIG_MPC85xx         /* MPC8540/60/55/41/48 family           */
 #define CONFIG_FSL_ELBC                /* FreeScale Enhanced LocalBus Cntlr    */
 #define CONFIG_FSL_LAW         /* FreeScale Local Access Window        */
 #define CONFIG_P2020           /* FreeScale P2020                      */
@@ -53,8 +52,6 @@
 
 /* Enable IRQs and watchdog with a 1000Hz system decrementer */
 #define CONFIG_CMD_IRQ
-#define CONFIG_SYS_HZ 1000
-
 
 /* -------------------------------------------------------------------- */
 
@@ -202,16 +199,16 @@
 /* -------------------------------------------------------------------- */
 
 /* Generic FreeScale hardware I2C support */
-#define CONFIG_HARD_I2C
-#define CONFIG_FSL_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED       400000
+#define CONFIG_SYS_FSL_I2C_SLAVE       0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET      0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED      400000
+#define CONFIG_SYS_FSL_I2C2_SLAVE      0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET     0x3100
+#define CONFIG_SYS_I2C_NOPROBES                { {0, 0x29} }
 #define CONFIG_CMD_I2C
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_OFFSET  0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
-
-/* I2C bus configuration */
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
 
 /* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */
 #define CONFIG_SYS_SPD_BUS_NUM 0
@@ -257,7 +254,7 @@
 /* -------------------------------------------------------------------- */
 
 /* FreeScale DDR2/3 SDRAM Controller */
-#define CONFIG_FSL_DDR2                /* Our SDRAM slot is DDR2               */
+#define CONFIG_SYS_FSL_DDR2            /* Our SDRAM slot is DDR2               */
 #define CONFIG_DDR_ECC         /* Enable ECC by default                */
 #define CONFIG_DDR_SPD         /* Detect DDR config from SPD EEPROM    */
 #define CONFIG_SPD_EEPROM      /* ...why 2 config variables for this?  */