ARM: highbank: change TEXT_BASE to 0x8000

[u-boot] / include / configs / M5253EVBE.h

diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h
index 206d1152ee47f0d16b0b9712e022f82cded231a6..dd8a56011f78876f8199cf0f1e66b1d18b9ca898 100644 (file)
--- a/include/configs/M5253EVBE.h
+++ b/include/configs/M5253EVBE.h
@@ -135,9 +135,8 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR       0x20000000
-#define CONFIG_SYS_INIT_RAM_END        0x10000 /* End of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE       0x10000 /* Size of used area in internal SRAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
@@ -181,9 +180,9 @@
 #define CONFIG_SYS_CACHELINE_SIZE      16
 
 #define ICACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
-                                        CONFIG_SYS_INIT_RAM_END - 8)
+                                        CONFIG_SYS_INIT_RAM_SIZE - 8)
 #define DCACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
-                                        CONFIG_SYS_INIT_RAM_END - 4)
+                                        CONFIG_SYS_INIT_RAM_SIZE - 4)
 #define CONFIG_SYS_ICACHE_INV          (CF_CACR_DCM)
 #define CONFIG_SYS_CACHE_ACR0          (CONFIG_SYS_FLASH_BASE | \
                                         CF_ADDRMASK(2) | \