Merge branch 'at91' of git://git.denx.de/u-boot-atmel

[u-boot] / include / configs / M5282EVB.h

diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index a8a265564d5e3ec0a9264e617d2425f302949f4d..6e0aa14d3a0945bc24757fc7f589f81bc0c75099 100644 (file)
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -64,6 +64,7 @@
  * Command line configuration.
  */
 #include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
@@ -165,7 +166,7 @@
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000
 #define        CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE          0xffe00000
+#define CONFIG_SYS_FLASH_BASE          CONFIG_SYS_CS0_BASE
 #define        CONFIG_SYS_INT_FLASH_BASE       0xf0000000
 #define CONFIG_SYS_INT_FLASH_ENABLE    0x21
 
@@ -209,21 +210,25 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE      16
 
+#define ICACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV          (CF_CACR_CINV + CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0          (CONFIG_SYS_SDRAM_BASE | \
+                                        CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+                                        CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR         (CF_CACR_CENB | CF_CACR_DISD | \
+                                        CF_CACR_CEIB | CF_CACR_DBWE | \
+                                        CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
-#define CONFIG_SYS_CS0_BASE            CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE            2*1024*1024
-#define CONFIG_SYS_CS0_WIDTH           16
-#define CONFIG_SYS_CS0_RO              0
-#define CONFIG_SYS_CS0_WS              6
-/*
-#define CONFIG_SYS_CS3_BASE            0xE0000000
-#define CONFIG_SYS_CS3_SIZE            1*1024*1024
-#define CONFIG_SYS_CS3_WIDTH           16
-#define CONFIG_SYS_CS3_RO              0
-#define CONFIG_SYS_CS3_WS              6
-*/
+#define CONFIG_SYS_CS0_BASE            0xFFE00000
+#define CONFIG_SYS_CS0_CTRL            0x00001980
+#define CONFIG_SYS_CS0_MASK            0x001F0001
+
 /*-----------------------------------------------------------------------
  * Port configuration
  */