DaVinci DM6467: Enhance board Support

[u-boot] / include / configs / M54451EVB.h

diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index a5acfd28460f53e8bc438c88a4f157956fa95849..37715c50c2492f9923a8dad97b6532cf43256e16 100644 (file)
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -220,12 +220,11 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR       0x80000000
-#define CONFIG_SYS_INIT_RAM_END        0x8000  /* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE       0x8000  /* Size of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM_CTRL       0x221
-#define CONFIG_SYS_GBL_DATA_SIZE       256     /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_GBL_DATA_OFFSET     ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_SBFHDR_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - 32)
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - 32)
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
@@ -245,7 +244,7 @@
 #define CONFIG_SYS_MEMTEST_END         ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 
 #ifdef CONFIG_CF_SBF
-#      define CONFIG_SYS_MONITOR_BASE  (TEXT_BASE + 0x400)
+#      define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_TEXT_BASE + 0x400)
 #else
 #      define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 #endif
@@ -309,6 +308,21 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE              16
 
+#define ICACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV          (CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CONFIG_SYS_DCACHE_INV          (CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2          (CONFIG_SYS_SDRAM_BASE | \
+                                        CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+                                        CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR         (CF_CACR_BEC | CF_CACR_IEC | \
+                                        CF_CACR_ICINVA | CF_CACR_EUSP)
+#define CONFIG_SYS_CACHE_DCACR         ((CONFIG_SYS_CACHE_ICACR | \
+                                        CF_CACR_DEC | CF_CACR_DDCM_P | \
+                                        CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */