Code cleanup; make several boards compile & link.

[u-boot] / include / configs / MPC8266ADS.h

diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h
index 9e8d732e2bd42f15d0b9ca18181b23340c965534..5b2a8a33e2dec77231c66fcd0a2d7fda7bcf4da2 100644 (file)
--- a/include/configs/MPC8266ADS.h
+++ b/include/configs/MPC8266ADS.h
@@ -38,7 +38,7 @@
    !!  0xfff00000                                                    !!
    !!  The CFG_HRCW_MASTER define below must also be changed to match !!
    !!                                                                 !!
-   !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 
+   !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
  */
 
 #ifndef __CONFIG_H
@@ -49,10 +49,10 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC8260         1       /* This is an MPC8260 CPU   */
-#define CONFIG_MPC8266ADS      1       /* ...on motorola ads board */
+#define CONFIG_MPC8260         1       /* This is an MPC8260 CPU       */
+#define CONFIG_MPC8266ADS      1       /* ...on motorola ADS board     */
 
-#define CONFIG_BOARD_PRE_INIT  1       /* Call board_pre_init  */
+#define CONFIG_BOARD_EARLY_INIT_F 1    /* Call board_early_init_f      */
 
 /* allow serial and ethaddr to be overwritten */
 #define CONFIG_ENV_OVERWRITE
@@ -175,7 +175,7 @@
 #define CONFIG_BOOT_ROOT_INITRD 0      /* Use ram disk for the root file system */
 #define CONFIG_BOOT_ROOT_NFS   1       /* Use a NFS mounted root file system */
 
-#if CONFIG_BOOT_ROOT_INITRD
+#ifdef CONFIG_BOOT_ROOT_INITRD
 #define CONFIG_BOOTCOMMAND \
        "version;" \
        "echo;" \
@@ -185,7 +185,7 @@
        "bootm"
 #endif /* CONFIG_BOOT_ROOT_INITRD */
 
-#if CONFIG_BOOT_ROOT_NFS
+#ifdef CONFIG_BOOT_ROOT_NFS
 #define CONFIG_BOOTCOMMAND \
        "version;" \
        "echo;" \
@@ -398,15 +398,15 @@
 /* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3)  */
 /* #define CFG_HRCW_MASTER 0x0cb23645 */
 
-/* This value should actually be situated in the first 256 bytes of the FLASH  
+/* This value should actually be situated in the first 256 bytes of the FLASH
        which on the standard MPC8266ADS board is at address 0xFF800000
        The linker script places it at 0xFFF00000 instead.
 
-       It still works, however, as long as the ADS board jumper JP3 is set to 
-       position 2-3 so the board is using the BCSR as Hardware Configuration Word 
+       It still works, however, as long as the ADS board jumper JP3 is set to
+       position 2-3 so the board is using the BCSR as Hardware Configuration Word
 
-       If you want to use the one defined here instead, ust copy the first 256 bytes from 
-       0xfff00000 to 0xff800000  (for 8MB flash) 
+       If you want to use the one defined here instead, ust copy the first 256 bytes from
+       0xfff00000 to 0xff800000  (for 8MB flash)
 
        - Rune
 
@@ -508,18 +508,19 @@
 #define CFG_MPTPR              0x00001900
 #define CFG_PSRT               0x00000021
 
-#define CFG_RESET_ADDRESS      0x04400000
+/* This address must not exist */
+#define CFG_RESET_ADDRESS      0xFCFFFF00
 
 /* PCI Memory map (if different from default map */
 #define CFG_PCI_SLV_MEM_LOCAL  CFG_SDRAM_BASE          /* Local base */
 #define CFG_PCI_SLV_MEM_BUS            0x00000000              /* PCI base */
 #define CFG_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
-                                PICMR_PREFETCH_EN)
+                                PICMR_PREFETCH_EN)
 
-/* 
+/*
  * These are the windows that allow the CPU to access PCI address space.
- * All three PCI master windows, which allow the CPU to access PCI 
- * prefetch, non prefetch, and IO space (see below), must all fit within 
+ * All three PCI master windows, which allow the CPU to access PCI
+ * prefetch, non prefetch, and IO space (see below), must all fit within
  * these windows.
  */
 
@@ -530,7 +531,7 @@
 #define CFG_PCI_MSTR1_LOCAL            0xF4000000              /* Local base */
 #define CFG_PCIMSK1_MASK               PCIMSK_64MB             /* Size of window */
 
-/* 
+/*
  * Master window that allows the CPU to access PCI Memory (prefetch).
  * This window will be setup with the first set of Outbound ATU registers
  * in the bridge.
@@ -542,7 +543,7 @@
 #define CFG_PCI_MSTR_MEM_SIZE  0x20000000          /* 512MB */
 #define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
 
-/* 
+/*
  * Master window that allows the CPU to access PCI Memory (non-prefetch).
  * This window will be setup with the second set of Outbound ATU registers
  * in the bridge.
@@ -554,7 +555,7 @@
 #define CFG_PCI_MSTR_MEMIO_SIZE     0x20000000          /* 512MB */
 #define CFG_POCMR1_MASK_ATTRIB      (POCMR_MASK_512MB | POCMR_ENABLE)
 
-/* 
+/*
  * Master window that allows the CPU to access PCI IO space.
  * This window will be setup with the third set of Outbound ATU registers
  * in the bridge.