Merge branch 'master' of git://git.denx.de/u-boot-arm

[u-boot] / include / configs / MPC8308RDB.h

diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index 8f0835f8f902fa497ba6ef4def9e48caacd084f9..2d48dde808478b71646549a6d37a4d3133eb9a2b 100644 (file)
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -37,6 +37,24 @@
 
 #define CONFIG_MISC_INIT_R
 
+/* new uImage format support */
+#define CONFIG_FIT                     1
+#define CONFIG_FIT_VERBOSE             1
+
+#define CONFIG_MMC     1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ESDHC_USE_PIO
+
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
 /*
  * On-board devices
  *
@@ -149,7 +167,8 @@
 
 #define CONFIG_SYS_DDR_CS0_BNDS        0x00000007
 #define CONFIG_SYS_DDR_CS0_CONFIG      (CSCONFIG_EN \
-                               | 0x00010000  /* ODT_WR to CSn */ \
+                               | CSCONFIG_ODT_RD_NEVER \
+                               | CSCONFIG_ODT_WR_ONLY_CURRENT \
                                | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
                                /* 0x80010102 */
 #define CONFIG_SYS_DDR_TIMING_3        0x00000000
@@ -184,7 +203,7 @@
                                /* 0x03600100 */
 #define CONFIG_SYS_DDR_SDRAM_CFG       (SDRAM_CFG_SREN \
                                | SDRAM_CFG_SDRAM_TYPE_DDR2 \
-                               | SDRAM_CFG_32_BE)
+                               | SDRAM_CFG_DBW_32)
                                /* 0x43080000 */
 
 #define CONFIG_SYS_DDR_SDRAM_CFG2      0x00401000 /* 1 posted refresh */
@@ -238,19 +257,18 @@
 #define CONFIG_SYS_LBLAWBAR0_PRELIM    CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_LBLAWAR0_PRELIM     (LBLAWAR_EN | LBLAWAR_8MB)
 
-#define CONFIG_SYS_BR0_PRELIM  (\
-               CONFIG_SYS_FLASH_BASE   /* Flash Base address */        |\
-               (2 << BR_PS_SHIFT)      /* 16 bit port size */          |\
-               BR_V)                   /* valid */
-#define CONFIG_SYS_OR0_PRELIM  ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
+                               | BR_PS_16      /* 16 bit port */ \
+                               | BR_MS_GPCM    /* MSEL = GPCM */ \
+                               | BR_V)         /* valid */
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
                                | OR_UPM_XAM \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_ACS_DIV2 \
                                | OR_GPCM_XACS \
                                | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX \
-                               | OR_GPCM_EHTR \
-                               | OR_GPCM_EAD)
+                               | OR_GPCM_TRLX_SET \
+                               | OR_GPCM_EHTR_SET)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1 /* number of banks */
 /* 127 64KB sectors and 8 8KB top sectors per device */
@@ -263,12 +281,13 @@
  * NAND Flash on the Local Bus
  */
 #define CONFIG_SYS_NAND_BASE   0xE0600000              /* 0xE0600000 */
+#define CONFIG_SYS_NAND_WINDOW_SIZE    (32 * 1024)     /* 0x00008000 */
 #define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_NAND_BASE \
-                               | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
-                               | BR_PS_8               /* 8 bit port */ \
+                               | BR_DECC_CHK_GEN       /* Use HW ECC */ \
+                               | BR_PS_8               /* 8 bit Port */ \
                                | BR_MS_FCM             /* MSEL = FCM */ \
                                | BR_V)                 /* valid */
-#define CONFIG_SYS_OR1_PRELIM  (0xFFFF8000             /* length 32K */ \
+#define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
                                | OR_FCM_CSCT \
                                | OR_FCM_CST \
                                | OR_FCM_CHT \
@@ -282,9 +301,22 @@
 
 #ifdef CONFIG_VSC7385_ENET
 #define CONFIG_TSEC2
+                                       /* VSC7385 Base address on CS2 */
 #define CONFIG_SYS_VSC7385_BASE                0xF0000000
-#define CONFIG_SYS_BR2_PRELIM          0xf0000801 /* VSC7385 Base address */
-#define CONFIG_SYS_OR2_PRELIM          0xfffe09ff /* VSC7385, 128K bytes*/
+#define CONFIG_SYS_VSC7385_SIZE                (128 * 1024) /* 0x00020000 */
+#define CONFIG_SYS_BR2_PRELIM          (CONFIG_SYS_VSC7385_BASE \
+                                       | BR_PS_8       /* 8-bit port */ \
+                                       | BR_MS_GPCM    /* MSEL = GPCM */ \
+                                       | BR_V)         /* valid */
+                                       /* 0xF0000801 */
+#define CONFIG_SYS_OR2_PRELIM          (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \
+                                       | OR_GPCM_CSNT \
+                                       | OR_GPCM_XACS \
+                                       | OR_GPCM_SCY_15 \
+                                       | OR_GPCM_SETA \
+                                       | OR_GPCM_TRLX_SET \
+                                       | OR_GPCM_EHTR_SET)
+                                       /* 0xFFFE09FF */
 /* Access window base at VSC7385 base */
 #define CONFIG_SYS_LBLAWBAR2_PRELIM    CONFIG_SYS_VSC7385_BASE
 /* Access window size 128K */
@@ -310,7 +342,6 @@
 
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
 /* Pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT       1
@@ -327,6 +358,19 @@
 #define CONFIG_SYS_I2C_OFFSET  0x3000
 #define CONFIG_SYS_I2C2_OFFSET 0x3100
 
+/*
+ * SPI on header J8
+ *
+ * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch)
+ * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins.
+ */
+#ifdef CONFIG_MPC8XXX_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_USE_SPIFLASH
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#endif
 
 /*
  * Board info - revision and where boot from