mpc83xx: convert all remaining boards over to 83XX_GENERIC_PCI

[u-boot] / include / configs / MPC832XEMDS.h

diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index bc56e682a75619cdfbbfbc382781ab69b78d799d..69289813a6fd718ec0f78dea59d07a698b2338f7 100644 (file)
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -8,7 +8,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.        See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -25,8 +25,8 @@
  */
 #define CONFIG_E300            1       /* E300 family */
 #define CONFIG_QE              1       /* Has QE */
-#define CONFIG_MPC83XX         1       /* MPC83xx family */
-#define CONFIG_MPC832X         1       /* MPC832x CPU specific */
+#define CONFIG_MPC83xx         1       /* MPC83xx family */
+#define CONFIG_MPC832x         1       /* MPC832x CPU specific */
 #define CONFIG_MPC832XEMDS     1       /* MPC832XEMDS board specific */
 #undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
 #undef CONFIG_PQ_MDS_PIB_ATM   /* QOC3 ATM card */
@@ -144,7 +144,7 @@
 #endif
 
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN         (384 * 1024)    /* Reserve 384 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN          (128 * 1024)    /* Reserved for malloc */
 
 /*
@@ -246,34 +246,8 @@
 #define CONFIG_SYS_LBC_LSRT    0x32000000      /* LB sdram refresh timer, about 6us */
 #define CONFIG_SYS_LBC_MRTPR   0x20000000      /* LB refresh timer prescal, 266MHz/32 */
 
-/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW    (3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH  (4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV  (7 << (31 - 4))
-
 #define CONFIG_SYS_LBC_LSDMR_COMMON    0x0063b723
 
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CONFIG_SYS_LBC_LSDMR_1         ( CONFIG_SYS_LBC_LSDMR_COMMON \
-                               | CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2         ( CONFIG_SYS_LBC_LSDMR_COMMON \
-                               | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3         ( CONFIG_SYS_LBC_LSDMR_COMMON \
-                               | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4         ( CONFIG_SYS_LBC_LSDMR_COMMON \
-                               | CONFIG_SYS_LBC_LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5         ( CONFIG_SYS_LBC_LSDMR_COMMON \
-                               | CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
-
 #endif
 
 /*
@@ -341,15 +315,15 @@
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CONFIG_SYS_PCI_MEM_BASE        0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS        CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE        0x10000000      /* 256M */
-#define CONFIG_SYS_PCI_MMIO_BASE       0x90000000
-#define CONFIG_SYS_PCI_MMIO_PHYS       CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE       0x10000000      /* 256M */
-#define CONFIG_SYS_PCI_IO_BASE         0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS         0xE0300000
-#define CONFIG_SYS_PCI_IO_SIZE         0x100000        /* 1M */
+#define CONFIG_SYS_PCI1_MEM_BASE       0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE       0x10000000      /* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE      0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS      CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE      0x10000000      /* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE                0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS                0xE0300000
+#define CONFIG_SYS_PCI1_IO_SIZE                0x100000        /* 1M */
 
 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL   CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_PCI_SLV_MEM_BUS     0x00000000
@@ -360,6 +334,8 @@
 
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP         /* do pci plug-and-play */
+#define CONFIG_83XX_GENERIC_PCI
+#define CONFIG_83XX_PCI_STREAMING
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
@@ -441,7 +417,7 @@
 #endif
 
 #if defined(CONFIG_SYS_RAMBOOT)
-    #undef CONFIG_CMD_ENV
+    #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
 
@@ -526,14 +502,14 @@
 
 #ifdef CONFIG_PCI
 /* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L      (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT6U      (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT6L      (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT6U      (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT6L      CONFIG_SYS_IBAT6L
 #define CONFIG_SYS_DBAT6U      CONFIG_SYS_IBAT6U
 /* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L      (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT7L      (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
                        BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT7U      (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT7U      (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT7L      CONFIG_SYS_IBAT7L
 #define CONFIG_SYS_DBAT7U      CONFIG_SYS_IBAT7U
 #else
@@ -562,9 +538,7 @@
 
 /*
  * Environment Configuration
- */
-
-#define CONFIG_ENV_OVERWRITE
+ */ #define CONFIG_ENV_OVERWRITE
 
 #if defined(CONFIG_UEC_ETH)
 #define CONFIG_HAS_ETH0