Merged MPC8349ADS and MPC8349EMDS ports into MPC8349EMDS port:

[u-boot] / include / configs / MPC8349EMDS.h

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 1a479805e0ad6bb22b629d0f1b54e347814b21e9..0300b0d949a47b507406be554e5a907f37094dfb 100644 (file)
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -29,7 +29,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define DEBUG
 #undef DEBUG
 
 /*
@@ -40,8 +39,8 @@
 #define CONFIG_MPC8349         1       /* MPC8349 specific */
 #define CONFIG_MPC8349EMDS     1       /* MPC8349EMDS board specific */
 
-/* FIXME: Real PCI support will come in a follow-up update. */
-#undef CONFIG_PCI
+#undef CONFIG_PCI              
+#undef CONFIG_MPC83XX_PCI2             /* support for 2nd PCI controller */
 
 #define PCI_66M
 #ifdef PCI_66M
@@ -53,8 +52,10 @@
 #ifndef CONFIG_SYS_CLK_FREQ
 #ifdef PCI_66M
 #define CONFIG_SYS_CLK_FREQ    66000000
+#define HRCWL_CSB_TO_CLKIN     HRCWL_CSB_TO_CLKIN_4X1
 #else
 #define CONFIG_SYS_CLK_FREQ    33000000
+#define HRCWL_CSB_TO_CLKIN     HRCWL_CSB_TO_CLKIN_8X1
 #endif
 #endif
 
@@ -69,7 +70,7 @@
 /*
  * DDR Setup
  */
-#define CONFIG_DDR_ECC                 /* only for ECC DDR module */
+#undef CONFIG_DDR_ECC                  /* only for ECC DDR module */
 #define CONFIG_DDR_ECC_CMD             /* use DDR ECC user commands */
 #define CONFIG_SPD_EEPROM              /* use SPD EEPROM for DDR setup*/
 
@@ -157,7 +158,7 @@
 /*
  * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
  */
-#define CFG_BCSR               0xF8000000
+#define CFG_BCSR               0xE2400000
 #define CFG_LBLAWBAR1_PRELIM   CFG_BCSR                /* Access window base at BCSR base */
 #define CFG_LBLAWAR1_PRELIM    0x8000000E              /* Access window size 32K */
 #define CFG_BR1_PRELIM         (CFG_BCSR|0x00000801)   /* Port-size=8bit, MSEL=GPCM */
@@ -165,7 +166,7 @@
 
 #define CONFIG_L1_INIT_RAM
 #define CFG_INIT_RAM_LOCK      1
-#define CFG_INIT_RAM_ADDR      0xE8000000              /* Initial RAM address */
+#define CFG_INIT_RAM_ADDR      0xFD000000              /* Initial RAM address */
 #define CFG_INIT_RAM_END       0x1000                  /* End of used area in RAM*/
 
 #define CFG_GBL_DATA_SIZE      0x100                   /* num bytes initial data */
@@ -322,18 +323,8 @@
 #define CFG_TSEC2_OFFSET 0x25000
 #define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET)
 
-/* IO Configuration */
-#define CFG_IO_CONF (\
-       IO_CONF_UART |\
-       IO_CONF_TSEC1 |\
-       IO_CONF_IRQ0 |\
-       IO_CONF_IRQ1 |\
-       IO_CONF_IRQ2 |\
-       IO_CONF_IRQ3 |\
-       IO_CONF_IRQ4 |\
-       IO_CONF_IRQ5 |\
-       IO_CONF_IRQ6 |\
-       IO_CONF_IRQ7 )
+/* USB */
+#define CFG_USE_MPC834XSYS_USB_PHY     1 /* Use SYS board PHY */
 
 /*
  * General PCI
@@ -341,21 +332,27 @@
  */
 #define CFG_PCI1_MEM_BASE      0x80000000
 #define CFG_PCI1_MEM_PHYS      CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE      0x20000000      /* 512M */
+#define CFG_PCI1_MEM_SIZE      0x10000000      /* 256M */
+#define CFG_PCI1_MMIO_BASE     0x90000000
+#define CFG_PCI1_MMIO_PHYS     CFG_PCI1_MMIO_BASE
+#define CFG_PCI1_MMIO_SIZE     0x10000000      /* 256M */
 #define CFG_PCI1_IO_BASE       0x00000000
-#define CFG_PCI1_IO_PHYS       0xe2000000
-#define CFG_PCI1_IO_SIZE       0x1000000       /* 16M */
+#define CFG_PCI1_IO_PHYS       0xE2000000
+#define CFG_PCI1_IO_SIZE       0x00100000      /* 1M */
 
 #define CFG_PCI2_MEM_BASE      0xA0000000
 #define CFG_PCI2_MEM_PHYS      CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE      0x20000000      /* 512M */
+#define CFG_PCI2_MEM_SIZE      0x10000000      /* 256M */
+#define CFG_PCI2_MMIO_BASE     0xB0000000
+#define CFG_PCI2_MMIO_PHYS     CFG_PCI2_MMIO_BASE
+#define CFG_PCI2_MMIO_SIZE     0x10000000      /* 256M */
 #define CFG_PCI2_IO_BASE       0x00000000
-#define CFG_PCI2_IO_PHYS       0xe3000000
-#define CFG_PCI2_IO_SIZE       0x1000000       /* 16M */
+#define CFG_PCI2_IO_PHYS       0xE2100000
+#define CFG_PCI2_IO_SIZE       0x00100000      /* 1M */
 
 #if defined(CONFIG_PCI)
 
-#define PCI_ALL_PCI1
+#define PCI_ONE_PCI1
 #if defined(PCI_64BIT)
 #undef PCI_ALL_PCI1
 #undef PCI_TWO_PCI1
@@ -512,35 +509,35 @@
 #define CFG_HRCW_LOW (\
        HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
        HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN_4X1 |\
+       HRCWL_CSB_TO_CLKIN |\
        HRCWL_VCO_1X2 |\
        HRCWL_CORE_TO_CSB_2X1)
 #elif 0 /*396/132*/
 #define CFG_HRCW_LOW (\
        HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
        HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN_2X1 |\
+       HRCWL_CSB_TO_CLKIN |\
        HRCWL_VCO_1X4 |\
        HRCWL_CORE_TO_CSB_3X1)
 #elif 0 /*264/132*/
 #define CFG_HRCW_LOW (\
        HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
        HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN_2X1 |\
+       HRCWL_CSB_TO_CLKIN |\
        HRCWL_VCO_1X4 |\
        HRCWL_CORE_TO_CSB_2X1)
 #elif 0 /*132/132*/
 #define CFG_HRCW_LOW (\
        HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
        HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN_2X1 |\
+       HRCWL_CSB_TO_CLKIN |\
        HRCWL_VCO_1X4 |\
        HRCWL_CORE_TO_CSB_1X1)
 #elif 0 /*264/264 */
 #define CFG_HRCW_LOW (\
        HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
        HRCWL_DDR_TO_SCB_CLK_1X1 |\
-       HRCWL_CSB_TO_CLKIN_4X1 |\
+       HRCWL_CSB_TO_CLKIN |\
        HRCWL_VCO_1X4 |\
        HRCWL_CORE_TO_CSB_1X1)
 #endif
@@ -578,7 +575,7 @@
 #define CFG_SICRL SICRL_LDP_A
 
 #define CFG_HID0_INIT  0x000000000
-#define CFG_HID0_FINAL CFG_HID0_INIT
+#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
 
 /* #define CFG_HID0_FINAL              (\
        HID0_ENABLE_INSTRUCTION_CACHE |\
@@ -605,25 +602,28 @@
 #define CFG_IBAT2U     (0)
 #endif
 
-/* IMMRBAR @ 0xE0000000 */
-#define CFG_IBAT3L     (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT3U     (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
-
-/* stack in DCACHE (no backing mem) @ 0xE8000000 */
-#define CFG_IBAT4L     (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT4U     (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#ifdef CONFIG_MPC83XX_PCI2
+#define CFG_IBAT3L     (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT3U     (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L     (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT4U     (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT3L     (0)
+#define CFG_IBAT3U     (0)
+#define CFG_IBAT4L     (0)
+#define CFG_IBAT4U     (0)
+#endif
 
-/* LBC SDRAM @ 0xF0000000 */
-#define CFG_IBAT5L     (CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT5U     (CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
+#define CFG_IBAT5L     (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U     (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP)
 
-/* BCSR  @ 0xF8000000 */
-#define CFG_IBAT6L     (CFG_BCSR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_IBAT6U     (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
+/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
+#define CFG_IBAT6L     (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT6U     (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
-/* FLASH @ 0xFE000000 */
-#define CFG_IBAT7L     (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT7U     (CFG_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP)
+#define CFG_IBAT7L     (0)
+#define CFG_IBAT7U     (0)
 
 #define CFG_DBAT0L     CFG_IBAT0L
 #define CFG_DBAT0U     CFG_IBAT0U